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Date:   Tue, 2 Nov 2021 09:42:41 +0100
From:   Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To:     Pali =?iso-8859-1?Q?Roh=E1r?= <pali@kernel.org>
Cc:     Russell King <linux@armlinux.org.uk>, Andrew Lunn <andrew@lunn.ch>,
        Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
        Gregory Clement <gregory.clement@bootlin.com>,
        Jason Gunthorpe <jgg@nvidia.com>,
        linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org,
        linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] PCI: Marvell: Update PCIe fixup
Message-ID: <20211102084241.GA6134@alpha.franken.de>
References: <20211101150405.14618-1-pali@kernel.org>
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On Mon, Nov 01, 2021 at 04:04:05PM +0100, Pali Roh?r wrote:
> - The code relies on rc_pci_fixup being called, which only happens
>   when CONFIG_PCI_QUIRKS is enabled, so add that to Kconfig. Omitting
>   this causes a booting failure with a non-obvious cause.
> - Update rc_pci_fixup to set the class properly, copying the
>   more modern style from other places
> - Correct the rc_pci_fixup comment
> 
> This patch just re-applies commit 1dc831bf53fd ("ARM: Kirkwood: Update
> PCI-E fixup") for all other Marvell platforms which use same buggy PCIe
> controller.
> [..]

> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 771ca53af06d..c8d51bd20b84 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -346,6 +346,7 @@ config MIPS_COBALT
>  	select CEVT_GT641XX
>  	select DMA_NONCOHERENT
>  	select FORCE_PCI
> +	select PCI_QUIRKS
>  	select I8253
>  	select I8259
>  	select IRQ_MIPS_CPU

this is enabled by default, via drivers/pci/Kconfig

config PCI_QUIRKS
        default y
        bool "Enable PCI quirk workarounds" if EXPERT
        help
          This enables workarounds for various PCI chipset bugs/quirks.
          Disable this only if your target machine is unaffected by PCI
          quirks.

> diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
> index 44be65c3e6bb..202f3a0bd97d 100644
> --- a/arch/mips/pci/fixup-cobalt.c
> +++ b/arch/mips/pci/fixup-cobalt.c
> @@ -36,6 +36,12 @@
>  #define VIA_COBALT_BRD_ID_REG  0x94
>  #define VIA_COBALT_BRD_REG_to_ID(reg)	((unsigned char)(reg) >> 4)
>  
> +/*
> + * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
> + * is operating as a root complex this needs to be switched to
> + * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
> + * the device. Decoding setup is handled by the orion code.
> + */
>  static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
>  {
>  	if (dev->devfn == PCI_DEVFN(0, 0) &&

this is not a PCIe controller, so how is this patch related ?

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]