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Subject: Re: [PATCH v3 08/21] cpufreq: amd: add acpi cppc function as the
 backend for legacy processors
To:     Huang Rui <ray.huang@amd.com>,
        "Rafael J . Wysocki" <rafael.j.wysocki@intel.com>,
        Viresh Kumar <viresh.kumar@linaro.org>,
        Shuah Khan <skhan@linuxfoundation.org>,
        Borislav Petkov <bp@suse.de>,
        Peter Zijlstra <peterz@infradead.org>,
        Ingo Molnar <mingo@kernel.org>,
        Giovanni Gherdovich <ggherdovich@suse.cz>,
        linux-pm@vger.kernel.org
Cc:     Deepak Sharma <deepak.sharma@amd.com>,
        Alex Deucher <alexander.deucher@amd.com>,
        Mario Limonciello <mario.limonciello@amd.com>,
        Steven Noonan <steven@valvesoftware.com>,
        Nathan Fontenot <nathan.fontenot@amd.com>,
        Jinzhou Su <Jinzhou.Su@amd.com>,
        Xiaojian Du <Xiaojian.Du@amd.com>,
        linux-kernel@vger.kernel.org, x86@kernel.org
References: <20211029130241.1984459-1-ray.huang@amd.com>
 <20211029130241.1984459-9-ray.huang@amd.com>
From:   Nathan Fontenot <nafonten@amd.com>
Message-ID: <33fe4c81-76f7-2de7-6b19-1c6b233b49aa@amd.com>
Date:   Tue, 2 Nov 2021 13:46:37 -0500
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 =?utf-8?B?NFFXZzU5aWFCanp2T2dlWUtYTmJvVG04Q2ZiaWlybjVyV0MwcGRRdEFlZWhx?=
 =?utf-8?B?aGZlTXhlUVlaNnp4SEpQN1pSY3FIN1I1MWFYMERjTHhVazFNM2FNTklrRHBC?=
 =?utf-8?B?TnRka1hjUlJ0Wm1xSDlqU2RhanlxWDZuU2JSV3NmOVhFc01JNmdmUlhXVVNY?=
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 =?utf-8?B?aW9SVVJtc0szeFNqL0paakZFeGxzQ05lWi9PZUY2OThTT3lvNVVCN25MKzRP?=
 =?utf-8?B?c0FxOGcwaHJYbm1WSnpZSkk1K2xTK05TYnJxMUdDSHNvR2E5V01ocndZYWNn?=
 =?utf-8?B?MVRvWVVuMVhZS3cxT0ZOaEt4QllScEhiTEZrRTk1a3lMUUlOb2pReHFxK1R0?=
 =?utf-8?B?ZHhXbjBjTE84R3BLVFNrbi8ySjFzNEorMHFaQloyOEN5WGJVRGc5bjlFWWdX?=
 =?utf-8?B?WGo2aHFwc2VJU2FibGN6Vm81ZEtDemtKbnpIeGpwblFZakVSNjFtelVuNENR?=
 =?utf-8?B?ZXlSam1xQStRY2ZEanZNQklxakg4ZzZ1QmRldmNuNHlhTzBpOHZ2eFlPb1o0?=
 =?utf-8?B?VUhpbXNwR3lkbGg0RG5HMUhLeGZjbi9iVGpyZE0wSE4wVEd6UXE1S29sN01D?=
 =?utf-8?B?Umg0UjBZNnJIa1RUTlhvZTZ3ak9kdlcvQ1hPam5xaGtzZS9nUFovOXhubnRM?=
 =?utf-8?B?L0pWMGVERHlVelNFZW1jZGRLMFJua20raHJYcE5SMGlkUnZtTTJjb0diZGRI?=
 =?utf-8?B?QXBxOGlUT0FucVZ1TzFJU1lublNIdHlPUWloVjVvQTVLRTV1SndNUFpJTVQr?=
 =?utf-8?B?WTJKM09mWjdiQmF1S1ZTTzlGaEdZY3I4NHFyVEpJc0tpUnltZ0w5dXJnR2pL?=
 =?utf-8?B?MXMyNEhHSHh0MmVYK2hoV0ppU3pjODZSWUZ5QkVScVpZaE1ZblJNd1BRdjNK?=
 =?utf-8?B?dHIzMWdmNEIydXBtT1BZRUNINldCaisxL0pWd0pXeU5lb1F2bTlGeW5hUURy?=
 =?utf-8?B?bmZRMWt5Si84OWlSanJ4WEpCRjRBb29LRCs5MDIwM0lVVkxDcHFXZk56TkVl?=
 =?utf-8?B?WEtIa0VFYUR1ZEZ0ay9qbzk3cDQ0ZHlPbWF4RU0rbzVlY2NEN1pyaGR2dGRq?=
 =?utf-8?B?WnlmN1VjNHNEbm1LcERadzIwRmhvK0FJclpHK1lEdnVSVXZ5Uzg1NW5hZGJU?=
 =?utf-8?B?U3h0ZFE2Z2o4blhQQzNKT0RxVVB5RW9BcUlDOFcvWE92RXN5Q255cm81OUV6?=
 =?utf-8?B?eTJ1dEJjQmZLd0hOd2RwV2NLT1FqdE1UdTJKZGpvc3hHTHYvc3hya3pJQ1hv?=
 =?utf-8?B?Z1U1M3ZYWUh0OHlCUTJFYWxQSTlIVTduYlZ0NFUrQlpva2NRNmpvSzJpQkdl?=
 =?utf-8?B?ZDFVNXEyRGNJdXkxR3ZtN1c1WTRqeHpCQ0tMNWVyWHJqUmpSOGVEOFZKNXFT?=
 =?utf-8?B?SjFCSVBXendCbzZkNFNVZGNDVnhZZk9wT2tHd0RnWHgrdkVzQzlBaWlXRENl?=
 =?utf-8?B?TUh3Q2pUZmxFWXZYRG9OVWFMQ2RaUldJUmhxYVk3WThNL0dBOWMxT3JTWkJk?=
 =?utf-8?Q?TV50yh4kEsHHiYb19PrCH2oK8F/qSDYvN9K053hAmQ=3D?=
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On 10/29/21 8:02 AM, Huang Rui wrote:
> In some old Zen based processors, they are using the shared memory that
> exposed from ACPI SBIOS.

With this you present two different approaches for support in the driver,
MSRs and shared memory. For processors using shared memory you use the 
shared memory defined in the ACPI tables but access the MSRs directly.

Is there any concern that the MSR registers (defined in patch 2/21) can
differ from what is defined in the ACPI tables?

Should you use the drivers/acpi interfaces for MSRs also?

-Nathan
 
> 
> Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>  drivers/cpufreq/amd-pstate.c | 58 ++++++++++++++++++++++++++++++++----
>  1 file changed, 53 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index 55ff03f85608..d399938d6d85 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -73,6 +73,19 @@ static inline int pstate_enable(bool enable)
>  	return wrmsrl_safe(MSR_AMD_CPPC_ENABLE, enable ? 1 : 0);
>  }
>  
> +static int cppc_enable(bool enable)
> +{
> +	int cpu, ret = 0;
> +
> +	for_each_online_cpu(cpu) {
> +		ret = cppc_set_enable(cpu, enable ? 1 : 0);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	return ret;
> +}
> +
>  DEFINE_STATIC_CALL(amd_pstate_enable, pstate_enable);
>  
>  static inline int amd_pstate_enable(bool enable)
> @@ -103,6 +116,24 @@ static int pstate_init_perf(struct amd_cpudata *cpudata)
>  	return 0;
>  }
>  
> +static int cppc_init_perf(struct amd_cpudata *cpudata)
> +{
> +	struct cppc_perf_caps cppc_perf;
> +
> +	int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
> +	if (ret)
> +		return ret;
> +
> +	WRITE_ONCE(cpudata->highest_perf, amd_get_highest_perf());
> +
> +	WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf);
> +	WRITE_ONCE(cpudata->lowest_nonlinear_perf,
> +		   cppc_perf.lowest_nonlinear_perf);
> +	WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf);
> +
> +	return 0;
> +}
> +
>  DEFINE_STATIC_CALL(amd_pstate_init_perf, pstate_init_perf);
>  
>  static inline int amd_pstate_init_perf(struct amd_cpudata *cpudata)
> @@ -120,6 +151,19 @@ static void pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf,
>  			      READ_ONCE(cpudata->cppc_req_cached));
>  }
>  
> +static void cppc_update_perf(struct amd_cpudata *cpudata,
> +			     u32 min_perf, u32 des_perf,
> +			     u32 max_perf, bool fast_switch)
> +{
> +	struct cppc_perf_ctrls perf_ctrls;
> +
> +	perf_ctrls.max_perf = max_perf;
> +	perf_ctrls.min_perf = min_perf;
> +	perf_ctrls.desired_perf = des_perf;
> +
> +	cppc_set_perf(cpudata->cpu, &perf_ctrls);
> +}
> +
>  DEFINE_STATIC_CALL(amd_pstate_update_perf, pstate_update_perf);
>  
>  static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata,
> @@ -346,7 +390,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
>  	/* It will be updated by governor */
>  	policy->cur = policy->cpuinfo.min_freq;
>  
> -	policy->fast_switch_possible = true;
> +	if (boot_cpu_has(X86_FEATURE_AMD_CPPC))
> +		policy->fast_switch_possible = true;
>  
>  	ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0],
>  				   FREQ_QOS_MIN, policy->cpuinfo.min_freq);
> @@ -397,7 +442,6 @@ static struct cpufreq_driver amd_pstate_driver = {
>  	.flags		= CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS,
>  	.verify		= amd_pstate_verify,
>  	.target		= amd_pstate_target,
> -	.adjust_perf    = amd_pstate_adjust_perf,
>  	.init		= amd_pstate_cpu_init,
>  	.exit		= amd_pstate_cpu_exit,
>  	.name		= "amd-pstate",
> @@ -421,10 +465,14 @@ static int __init amd_pstate_init(void)
>  		return -EEXIST;
>  
>  	/* capability check */
> -	if (!boot_cpu_has(X86_FEATURE_AMD_CPPC)) {
> -		pr_debug("%s, AMD CPPC MSR based functionality is not supported\n",
> +	if (boot_cpu_has(X86_FEATURE_AMD_CPPC)) {
> +		pr_debug("%s, AMD CPPC MSR based functionality is supported\n",
>  			 __func__);
> -		return -ENODEV;
> +		amd_pstate_driver.adjust_perf = amd_pstate_adjust_perf;
> +	} else {
> +		static_call_update(amd_pstate_enable, cppc_enable);
> +		static_call_update(amd_pstate_init_perf, cppc_init_perf);
> +		static_call_update(amd_pstate_update_perf, cppc_update_perf);
>  	}
>  
>  	/* enable amd pstate feature */
>