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Subject: Re: [PATCH v1 1/4] clk: qcom: clk-alpha-pll: Increase PLL lock detect poll time
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     Rajendra Nayak <rnayak@codeaurora.org>,
        linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org, robh@kernel.org, robh+dt@kernel.org,
        Taniya Das <tdas@codeaurora.org>
To:     Michael Turquette <mturquette@baylibre.com>,
        Taniya Das <tdas@codeaurora.org>
Date:   Tue, 02 Nov 2021 14:56:14 -0700
Message-ID: <163589017472.2993099.8634048687805619874@swboyd.mtv.corp.google.com>
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Quoting Taniya Das (2021-11-02 02:56:50)
> PLL poll for lock detection can take more than 100us for certain type

What types of PLLs? Is this fixing something that's broken? Or fixing a
future problem?

> of PLLs, thus update to 200us.
>=20

Does it needs a Fixes tag?

> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> ---
>  drivers/clk/qcom/clk-alpha-pll.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>=20
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alph=
a-pll.c
> index eaedcce..7cf6cfa 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -204,7 +204,7 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u3=
2 mask, bool inverse,
>         if (ret)
>                 return ret;
>=20
> -       for (count =3D 100; count > 0; count--) {
> +       for (count =3D 200; count > 0; count--) {
>                 ret =3D regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val=
);
>                 if (ret)