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Wed, 3 Nov 2021 01:15:00 +0000 Received: from [172.17.173.69] (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 3 Nov 2021 01:14:58 +0000 Subject: Re: [RFC v2 03/11] hte: Add tegra194 HTE kernel provider To: Randy Dunlap , , , , , , , , , , , References: <20210930232617.6396-1-dipenp@nvidia.com> <20210930232617.6396-4-dipenp@nvidia.com> X-Nvconfidentiality: public From: Dipen Patel Message-ID: Date: Tue, 2 Nov 2021 18:15:56 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Content-Language: en-US X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 69341790-74d0-4ac6-a7d6-08d99e675b9f X-MS-TrafficTypeDiagnostic: DM6PR12MB2761: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Nov 2021 01:15:00.3886 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 69341790-74d0-4ac6-a7d6-08d99e675b9f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2761 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Randy, Thanks for the comments. I will implement changes in RFC V3. Best Regards, Dipen Patel On 10/1/21 5:07 PM, Randy Dunlap wrote: > On 9/30/21 4:26 PM, Dipen Patel wrote: >> diff --git a/Documentation/hte/tegra194-hte.rst b/Documentation/hte/tegra194-hte.rst >> new file mode 100644 >> index 000000000000..fb229bda2408 >> --- /dev/null >> +++ b/Documentation/hte/tegra194-hte.rst >> @@ -0,0 +1,56 @@ >> +HTE Kernel provider driver >> +========================== >> + >> +Description >> +----------- >> +The Nvidia tegra194 HTE provider driver implements two GTE >> +(Generic Timestamping Engine) instances 1) GPIO GTE and 2) LIC IRQ GTE. The > >                                  instances:                                ^^Drop "The" > >> +both GTEs instances get the timestamp from the system counter TSC which has > >    Both > >> +31.25MHz clock rate, and the driver converts clock tick rate to nano seconds > >                                                                    nanoseconds > >> +before storing it as timestamp value. >> + >> +GPIO GTE >> +-------- >> + >> +This GTE instance timestamps GPIO in real time, for that to happen GPIO > >                                              time. For > >> +needs to be configured as input and IRQ needs to ba enabled. The only always on > >                                                     be > >> +(AON) gpio controller instance supports timestamping GPIOs in realtime and it > >          GPIO                                                    real time {or change >                            the instance 3 lines above to be "realtime"} > >> +has 39 GPIO lines. The GPIO GTE and AON GPIO controller are tightly coupled as >> +it requires very specific bits to be set in GPIO config register before GPIO> +GTE can be used. The GPIO GTE functionality is accessed from the GPIOLIB >> +framework for the in kernel and userspace consumers. In the later case, > >                      in-kernel                                 latter > >> +requests go through GPIOLIB CDEV framework. The below APIs are added in GPIOLIB >> +framework to access HTE subsystem and GPIO GTE. >> + >> +.. kernel-doc:: drivers/gpio/gpiolib.c >> +   :functions: gpiod_req_hw_timestamp_ns gpiod_rel_hw_timestamp_ns >> + >> +There is hte-tegra194-gpio-test.c, located in ``drivers/hte/`` directory, test >> +driver which demonstrates above APIs for the Jetson AGX platform. >> + >> +For userspace consumers, GPIO_V2_LINE_FLAG_EVENT_CLOCK_HARDWARE flag must be >> +specifed during IOCTL calls, refer ``tools/gpio/gpio-event-mon.c``, which > >    specified             calls. Refer to > >> +returns the timestamp in nano second. > >                             nanoseconds. > >> + >> +LIC IRQ GTE >> +----------- >> + >> +This GTE instance timestamp LIC IRQ lines in real time. There are 352 IRQ > >                      timestamps                 ^^^^^^^^^ {be consistent} >   (also (repeating a prior email) define "LIC") > >> +lines which this instance can help timestamp realtime. The hte devicetree > >                              can add timestamps to in realtime. > >> +binding described at ``Documentation/devicetree/bindings/hte/`` gives out > >                                                                    provides an > >> +example how consumer can request IRQ line, since it is one to one mapping, > >    example of how a consumer can request an IRQ line. Since it is a one-to-one mapping, > >> +consumers can simply specify IRQ number that they are interested in. There is > >                         specify the IRQ number > >> +no userspace consumer support for this GTE instance. The sample test code >> +hte-tegra194-irq-test.c, located in ``drivers/hte/`` directory, > >                                     in the > >> +demonstrates how to use IRQ GTE instance. The below is sample device tree > >                 how to use an IRQ GTE instance. > >> +snippet code for the test driver:: >> + >> + tegra_hte_irq_test { >> +        compatible = "nvidia,tegra194-hte-irq-test"; >> +        htes = <&tegra_hte_lic 0x19>; >> +        hte-names = "hte-lic"; >> + }; >> + >> +The provider source code of both IRQ and GPIO GTE instances is locate at > >                                                                   located > >> +``drivers/hte/hte-tegra194.c``. >> + > >