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From:   Richard Zhu <hongxing.zhu@nxp.com>
To:     Rob Herring <robh@kernel.org>
CC:     "l.stach@pengutronix.de" <l.stach@pengutronix.de>,
        Marcel Ziswiler <marcel.ziswiler@toradex.com>,
        "tharvey@gateworks.com" <tharvey@gateworks.com>,
        "kishon@ti.com" <kishon@ti.com>,
        "vkoul@kernel.org" <vkoul@kernel.org>,
        "galak@kernel.crashing.org" <galak@kernel.crashing.org>,
        "shawnguo@kernel.org" <shawnguo@kernel.org>,
        "linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "kernel@pengutronix.de" <kernel@pengutronix.de>,
        dl-linux-imx <linux-imx@nxp.com>
Subject: RE: [PATCH v5 2/8] dt-bindings: phy: Add imx8 pcie phy driver support
Thread-Topic: [PATCH v5 2/8] dt-bindings: phy: Add imx8 pcie phy driver
 support
Thread-Index: AQHXz5WHLrz9Vu7bJUqGSfOlmFnxU6vwcZQAgACcxCA=
Date:   Wed, 3 Nov 2021 02:07:54 +0000
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> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Wednesday, November 3, 2021 12:41 AM
> To: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: l.stach@pengutronix.de; Marcel Ziswiler
> <marcel.ziswiler@toradex.com>; tharvey@gateworks.com;
> kishon@ti.com; vkoul@kernel.org; galak@kernel.crashing.org;
> shawnguo@kernel.org; linux-phy@lists.infradead.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx
> <linux-imx@nxp.com>
> Subject: Re: [PATCH v5 2/8] dt-bindings: phy: Add imx8 pcie phy driver
> support
>=20
> On Tue, Nov 02, 2021 at 10:32:29AM +0800, Richard Zhu wrote:
> > Add dt-binding for the standalone i.MX8 PCIe PHY driver.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> > Reviewed-by: Tim Harvey <tharvey@gateworks.com>
> > Tested-by: Tim Harvey <tharvey@gateworks.com>
> > ---
> >  .../bindings/phy/fsl,imx8-pcie-phy.yaml       | 95
> +++++++++++++++++++
> >  1 file changed, 95 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> > b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> > new file mode 100644
> > index 000000000000..b9f89e343b0b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> > @@ -0,0 +1,95 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> >
> +https://eur01.safelinks.protection.outlook.com/?url=3Dhttp%3A%2F%2Fde
> vi
> >
> +cetree.org%2Fschemas%2Fphy%2Ffsl%2Cimx8-pcie-phy.yaml%23&amp
> ;data=3D04%
> >
> +7C01%7Chongxing.zhu%40nxp.com%7C1364bc88f1f84bac546708d99e1
> f8542%7C68
> >
> +6ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6377146804867737
> 07%7CUnknown
> >
> +%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik
> 1haWwiLC
> >
> +JXVCI6Mn0%3D%7C1000&amp;sdata=3DiEptMTlSVOTBuZCQNAKj6dyMFU
> fuBRnSt24nB6h
> > +Z9Lc%3D&amp;reserved=3D0
> > +$schema:
> >
> +https://eur01.safelinks.protection.outlook.com/?url=3Dhttp%3A%2F%2Fde
> vi
> >
> +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&amp;data=3D04%7C01%
> 7Chongxing.
> >
> +zhu%40nxp.com%7C1364bc88f1f84bac546708d99e1f8542%7C686ea1d
> 3bc2b4c6fa9
> >
> +2cd99c5c301635%7C0%7C0%7C637714680486773707%7CUnknown%7
> CTWFpbGZsb3d8e
> >
> +yJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn
> 0%3D%7C1
> >
> +000&amp;sdata=3DQ9S%2BP%2B8hliF4led7BdtytbPNzLH5pKLEoMjxhFIeg9
> M%3D&amp;
> > +reserved=3D0
> > +
> > +title: Freescale i.MX8 SoC series PCIe PHY Device Tree Bindings
> > +
> > +maintainers:
> > +  - Richard Zhu <hongxing.zhu@nxp.com>
> > +
> > +properties:
> > +  "#phy-cells":
> > +    const: 0
> > +
> > +  compatible:
> > +    enum:
> > +      - fsl,imx8mm-pcie-phy
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    items:
> > +      - description: PHY module clock
>=20
> The description doesn't really add much. Just 'maxItems: 1'.
[Richard Zhu] Okay, would add maxItems: 1. And remove the original items an=
d
 description. Thanks.
>=20
> > +
> > +  clock-names:
> > +    items:
> > +      - const: ref
> > +
> > +  resets:
> > +    items:
> > +      - description: Phandles to PCIe-related reset lines exposed by
> SRC
> > +          IP block.
>=20
> More than 1 phandle? The schema says only 1. Again, for only 1, you can
> use just 'maxItems: 1'.
[Richard Zhu] It's just only 1. Okay, the original items and descriptions w=
ould
 be replaced by 'maxItems: 1'. Thanks.
>=20
> > +
> > +  reset-names:
> > +    items:
> > +      - const: pciephy
> > +
> > +  fsl,refclk-pad-mode:
> > +    description: |
> > +      Specifies the mode of the refclk pad used. It can be
> UNUSED(PHY
> > +      refclock is derived from SoC internal source), INPUT(PHY
> refclock
> > +      is provided externally via the refclk pad) or OUTPUT(PHY
> refclock
> > +      is derived from SoC internal source and provided on the refclk
> pad).
> > +      Refer include/dt-bindings/phy/phy-imx8-pcie.h for the
> constants
> > +      to be used.
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    enum: [ 0, 1, 2 ]
> > +
> > +  fsl,tx-deemph-gen1:
> > +    description: Gen1 De-emphasis value (optional required).
>=20
> Optional or required?
[Richard Zhu] It's optional. Would simple it and below later. Thanks.

>=20
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    default: 0
> > +
> > +  fsl,tx-deemph-gen2:
> > +    description: Gen2 De-emphasis value (optional required).
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    default: 0
> > +
> > +  fsl,clkreq-unsupported:
> > +    type: boolean
> > +    description: A boolean property indicating the CLKREQ# signal is
> > +      not supported in the board design (optional)
> > +
> > +required:
> > +  - "#phy-cells"
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +  - clock-names
> > +  - fsl,refclk-pad-mode
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/imx8mm-clock.h>
> > +    #include <dt-bindings/phy/phy-imx8-pcie.h>
> > +    #include <dt-bindings/reset/imx8mq-reset.h>
> > +
> > +    pcie_phy: pcie-phy@32f00000 {
> > +            compatible =3D "fsl,imx8mm-pcie-phy";
> > +            reg =3D <0x32f00000 0x10000>;
> > +            clocks =3D <&clk IMX8MM_CLK_PCIE1_PHY>;
> > +            clock-names =3D "ref";
> > +            assigned-clocks =3D <&clk IMX8MM_CLK_PCIE1_PHY>;
> > +            assigned-clock-rates =3D <100000000>;
> > +            assigned-clock-parents =3D <&clk
> IMX8MM_SYS_PLL2_100M>;
> > +            resets =3D <&src IMX8MQ_RESET_PCIEPHY>;
> > +            reset-names =3D "pciephy";
> > +            fsl,refclk-pad-mode =3D
> <IMX8_PCIE_REFCLK_PAD_INPUT>;
> > +            #phy-cells =3D <0>;
> > +    };
> > +...
> > --
> > 2.25.1
> >
> >