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Date:   Wed, 3 Nov 2021 14:49:07 +0000 (GMT)
From:   "Maciej W. Rozycki" <macro@orcam.me.uk>
To:     =?UTF-8?Q?Pali_Roh=C3=A1r?= <pali@kernel.org>
cc:     Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        Russell King <linux@armlinux.org.uk>,
        Andrew Lunn <andrew@lunn.ch>,
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        Gregory Clement <gregory.clement@bootlin.com>,
        Jason Gunthorpe <jgg@nvidia.com>,
        =?UTF-8?Q?Marek_Beh=C3=BAn?= <kabel@kernel.org>,
        linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org,
        linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] PCI: Marvell: Update PCIe fixup
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On Tue, 2 Nov 2021, Pali Rohár wrote:

> Hello Maciej! Thank you very much for the explanation!

 You are welcome!

> I'm surprised that Marvell copied this 20 years old MIPS Galileo PCI
> logic into followup ARM SoC PCIe IPs (and later also into recent ARM64
> A3720 SoC PCIe IP), removed configuration of PCI class code via
> strapping pins and let default PCI class code value to Memory device,
> even also when PCIe controller is running in Root Complex mode. And so
> correction can be done only from "CPU bus".

 Still the bootstrap firmware (say U-boot, as I can see it mentioned in 
your reference) can write the correct value to the class code register.  
Or can it?

 I guess you can try it and report your findings back.  You can poke at 
PCI/e registers directly from U-boot (`pci write.w', etc.) as with any 
reasonable firmware monitor, no need to write code; I guess you probably 
know that already.

 I have no such hardware and I have no incentive to chase documentation 
for it even if public copies are available for the affected devices.  
Also you say it's IP rather than actual discrete chips as it used to be 
with the Galileo system controllers, so it could be up to the customer to 
get the IP wired/configured correctly.

> Maciej, if I had known that you have this kind of information I would
> have written you year ago :-)

 Well, I have all kinds of information.

  Maciej