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Date:   Wed, 3 Nov 2021 14:59:20 +0000 (GMT)
From:   "Maciej W. Rozycki" <macro@orcam.me.uk>
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cc:     Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
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Subject: Re: [PATCH] PCI: Marvell: Update PCIe fixup
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On Tue, 2 Nov 2021, Pali Rohár wrote:

> So the conclusion is that there is also some RESET configuration via
> BootCS (I have no idea what it is or was). And default value (when RESET
> configuration is not used) is always "Memory controller" due to
> existence of "broken PC BIOSes" (probably x86).

 BootCS is one of the chip selects for the memory/device bus (AD bus), one 
of the three (or four in dual-PCI implementations), along with the SysAD 
bus and the PCI bus(es), interconnected, which is where DRAM sits as well 
as possibly other locally accessed devices with the Galileo system 
controllers.  See Figure 5 on page 23 of the GT-64111 document.

  Maciej