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Rozycki" Cc: Thomas Bogendoerfer , Russell King , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Jason Gunthorpe , Marek =?utf-8?B?QmVow7pu?= , linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] PCI: Marvell: Update PCIe fixup Message-ID: <20211103150316.6vjtycnak5nkkiuz@pali> References: <20211101150405.14618-1-pali@kernel.org> <20211102084241.GA6134@alpha.franken.de> <20211102090246.unmbruykfdjabfga@pali> <20211102094700.GA7376@alpha.franken.de> <20211102100034.rhcb3k2jvr6alm6y@pali> <20211102125843.sqsusis4krnmhorq@pali> <20211102144929.c5wt5pbl42ocrxly@pali> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: NeoMutt/20180716 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wednesday 03 November 2021 14:49:07 Maciej W. Rozycki wrote: > On Tue, 2 Nov 2021, Pali Rohár wrote: > > > Hello Maciej! Thank you very much for the explanation! > > You are welcome! > > > I'm surprised that Marvell copied this 20 years old MIPS Galileo PCI > > logic into followup ARM SoC PCIe IPs (and later also into recent ARM64 > > A3720 SoC PCIe IP), removed configuration of PCI class code via > > strapping pins and let default PCI class code value to Memory device, > > even also when PCIe controller is running in Root Complex mode. And so > > correction can be done only from "CPU bus". > > Still the bootstrap firmware (say U-boot, as I can see it mentioned in > your reference) can write the correct value to the class code register. > Or can it? Yes, it can. And I have already sent patches to do it.