Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Date:   Wed, 3 Nov 2021 11:14:06 -0500
From:   Han Xu <han.xu@nxp.com>
To:     Christian Eggers <ceggers@arri.de>
Cc:     Michael Trimarchi <michael@amarulasolutions.com>,
        Miquel Raynal <miquel.raynal@bootlin.com>,
        Stefan Riedmueller <S.Riedmueller@phytec.de>,
        Greg Ungerer <gerg@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Christian Hemp <C.Hemp@phytec.de>,
        Boris Brezillon <bbrezillon@kernel.org>,
        Richard Weinberger <richard@nod.at>,
        Vignesh Raghavendra <vigneshr@ti.com>,
        linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
        stable@vger.kernel.org
Subject: Re: [PATCH 2/2] gpmi-nand: Add ERR007117 protection for
 nfc_apply_timings
Message-ID: <20211103161406.w4mk6rqhnajakstc@umbrella>
References: <20211102202022.15551-1-ceggers@arri.de>
 <20211102202022.15551-2-ceggers@arri.de>
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <20211102202022.15551-2-ceggers@arri.de>
User-Agent: NeoMutt/20171215
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?GBuU/KcLy+8XwAYCWXfzTw/885O3pF+8f4zX4Cl2+hFfd9sWgu1/NBGGvNfq?=
 =?us-ascii?Q?fa32a0XJ0BYTyq9GjddEqP6w03QRm4w7kEIzfbvQzx3kOH+SSEJZ3I3NrYzy?=
 =?us-ascii?Q?CITOMfLt56Y+oNNbwlUwUTUeVjm1azhrkl+7rv5HwXOXT/yRQyyONUVgiksr?=
 =?us-ascii?Q?9WYrYGocIKr59f2PBmoDwXNAIxQjkG4vi8kyXzMUxdR6B6Lhz1qquDhFyYL0?=
 =?us-ascii?Q?i0PULMz+jwMCl85gtIZVc+19IJ5Cedxf5ue5AjS8sIi1DFiwBPokxnA1I2Is?=
 =?us-ascii?Q?8pFWpgcs9Lk5r2YW2kXxPpLVdPzBEqyP5uxpKzVavuQnoMVBdUa0bJ+jCc2M?=
 =?us-ascii?Q?EZb9QyeS1dz44WiP/qpqBOBbm94owr9dbxdTlWRiAMyDSgUdErZ0pj1bpJQS?=
 =?us-ascii?Q?cIxndfmiAqCYKrZ/Gt4hE+k+0teRHP0R+YkIyRMqmNUCiHPvgdxrf+PMEriW?=
 =?us-ascii?Q?1X5Hqc/5Aoxqqlj/1d0HQidnEFbbffFRKGcKA8WH5DImV3bwUUexf3vgSZXy?=
 =?us-ascii?Q?80Y+nszct7IWneufu1MVh2yoPsZkEsrvirnV+6Blqgis/8gozs7TzYQWRZaK?=
 =?us-ascii?Q?CXsxO2jRFm8T4RFarEE7hvb16ZpVkxEFUqWhjPSR3EMhT+L/F/j7Fiqk3TCG?=
 =?us-ascii?Q?fb+7vKuji0f19rkuHCmncqEX6qglHbeIvcLEimZGUz5GyZr+9qiakXJZ1HcD?=
 =?us-ascii?Q?3FQiwz2XflXoCFscsK+sh9Wt7ftfGkZrW9EevU1nj2k2yPzuFSX5nq2KpvXO?=
 =?us-ascii?Q?99I4h4UqTD/crjywEMYDHqVJLBoPspDbG3tyCp2/t228fQIlXUL/OQ/BYx//?=
 =?us-ascii?Q?i4G6XagnwSmBr5jjDy7+RCZBVZw/98WbFLSLypT4AoEeQ85RkhShlklXLIoY?=
 =?us-ascii?Q?yKWt6Ayzz7w/P++wum7XJLfsRlXNfm9O1vV8O2tbYSaPwJXqZJw5nutArEIt?=
 =?us-ascii?Q?qwgdrIrMZ8Bd2jBJSz26oFvSEd0+w7dsIDEeo7iZafo9ygxlDf+feVEeMl4r?=
 =?us-ascii?Q?AyT2wqtHaMFzwh8gbtWo+VlqKkwpjLHMuR0hs5CgIuw136fTYUaj1yPlUdW2?=
 =?us-ascii?Q?3AjBiSTykPFORFWaSeYHeEfmKBeWpEwsYHMqdZyU5XJ+Vkk5T3H6l+unXp+M?=
 =?us-ascii?Q?Z+6QGK04cCGbCjzK/+U3svPv3KTTmhyoPgyXh8kNo7shH5eiYlOzeF2zu/t/?=
 =?us-ascii?Q?lZD7xmz+HJdrE+W+6od93r9ANb6+YPhNNe8vOkWWFkoF941GPzSv13pM107J?=
 =?us-ascii?Q?N2EUVGRRHUGX0k3DOAz5KhLgJYfQb6HK/tiw0xtJvXlouJJyw+nroAk3BV55?=
 =?us-ascii?Q?bTbbwdE5awh+tGyLJniSZ4anv0DGn6wjBlSMoeAEEfUdV/BSWbG7wa1siIQg?=
 =?us-ascii?Q?oLuXt0up9MbBQAgNWT90HJUCfGb6FkO4mOFHxov/pL8xwYJy9FY5g/JnMd0N?=
 =?us-ascii?Q?zGCR38hNsFhEPi3RUhe7TW+O4/IkTQuiGW5CM28echuvgcQM7YI62xc0YLJs?=
 =?us-ascii?Q?duaxPaS/SCPV/0hjN1CFtS5l5PGxvphPzcHJTmJaAb/pHXOVEKg0/pMMZTnN?=
 =?us-ascii?Q?ED7BQHwmpK0GBFZxnFI=3D?=
X-OriginatorOrg: nxp.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 9d2a3be1-7922-4566-cace-08d99ee4f978
X-MS-Exchange-CrossTenant-AuthSource: DU2PR04MB8774.eurprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Nov 2021 16:14:12.6085
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: MCAERhwvWE1a2FvgDZmIBQee3b7jeCXIY9mahUFelbFYZWNwh/Iwn6OZGroj0+Tp
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR04MB9273
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On 21/11/02 09:20PM, Christian Eggers wrote:
> gpmi_io clock needs to be gated off when changing the parent/dividers of
> enfc_clk_root (i.MX6Q/i.MX6UL) respectively qspi2_clk_root (i.MX6SX).
> Otherwise this rate change can lead to an unresponsive GPMI core which
> results in DMA timeouts and failed driver probe:
> 
> [    4.072318] gpmi-nand 112000.gpmi-nand: DMA timeout, last DMA
> ...
> [    4.370355] gpmi-nand 112000.gpmi-nand: Chip: 0, Error -110
> ...
> [    4.375988] gpmi-nand 112000.gpmi-nand: Chip: 0, Error -22
> [    4.381524] gpmi-nand 112000.gpmi-nand: Error in ECC-based read: -22
> [    4.387988] gpmi-nand 112000.gpmi-nand: Chip: 0, Error -22
> [    4.393535] gpmi-nand 112000.gpmi-nand: Chip: 0, Error -22
> ...
> 
> Other than stated in i.MX 6 erratum ERR007117, it should be sufficient
> to gate only gpmi_io because all other bch/nand clocks are derived from
> different clock roots.
> 
> The i.MX6 reference manuals state that changing clock muxers can cause
> glitches but are silent about changing dividers. But tests showed that
> these glitches can definitely happen on i.MX6ULL. For i.MX7D/8MM in turn,
> the manual guarantees that no glitches can happen when changing
> dividers.
> 
> Co-developed-by: Stefan Riedmueller <s.riedmueller@phytec.de>
> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
> Signed-off-by: Christian Eggers <ceggers@arri.de>
> Cc: stable@vger.kernel.org
> ---
> Changelog:
> -----------
> RFC --> v1
> - added comment about clock divider behavior on the different i.MX series
> - perform clock gating also on i.MX6SX
> - only gate gpmi_io clock. Other GPMI/BCH clocks are not affected when
>   ENFC_CLK_ROOT divides are changes
> - add error checking for clk_set_rate()
> - Cc: stable@vger.kernel.org
> 
>  drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c | 28 +++++++++++++++++++---
>  1 file changed, 25 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
> index a1f7000f033e..6e9f7d80ef8b 100644
> --- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
> +++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
> @@ -713,14 +713,32 @@ static void gpmi_nfc_compute_timings(struct gpmi_nand_data *this,
>  			      (use_half_period ? BM_GPMI_CTRL1_HALF_PERIOD : 0);
>  }
>  
> -static void gpmi_nfc_apply_timings(struct gpmi_nand_data *this)
> +static int gpmi_nfc_apply_timings(struct gpmi_nand_data *this)
>  {
>  	struct gpmi_nfc_hardware_timing *hw = &this->hw;
>  	struct resources *r = &this->resources;
>  	void __iomem *gpmi_regs = r->gpmi_regs;
>  	unsigned int dll_wait_time_us;
> +	int ret;
> +
> +	/* Clock dividers do NOT guarantee a clean clock signal on its output
> +	 * during the change of the divide factor on i.MX6Q/UL/SX. On i.MX7/8,
> +	 * all clock dividers provide these guarantee.
> +	 */
> +	if (GPMI_IS_MX6Q(this) || GPMI_IS_MX6SX(this))
> +		clk_disable_unprepare(r->clock[0]);
> +
> +	ret = clk_set_rate(r->clock[0], hw->clk_rate);
> +	if (ret) {
> +		dev_err(this->dev, "cannot set clock rate to %lu Hz: %d\n", hw->clk_rate, ret);
> +		return ret;
> +	}
>  
> -	clk_set_rate(r->clock[0], hw->clk_rate);
> +	if (GPMI_IS_MX6Q(this) || GPMI_IS_MX6SX(this)) {
> +		ret = clk_prepare_enable(r->clock[0]);
> +		if (ret)
> +			return ret;
> +	}
>  
>  	writel(hw->timing0, gpmi_regs + HW_GPMI_TIMING0);
>  	writel(hw->timing1, gpmi_regs + HW_GPMI_TIMING1);
> @@ -739,6 +757,8 @@ static void gpmi_nfc_apply_timings(struct gpmi_nand_data *this)
>  
>  	/* Wait for the DLL to settle. */
>  	udelay(dll_wait_time_us);
> +
> +	return 0;
>  }
>  
>  static int gpmi_setup_interface(struct nand_chip *chip, int chipnr,
> @@ -2271,7 +2291,9 @@ static int gpmi_nfc_exec_op(struct nand_chip *chip,
>  	 */
>  	if (this->hw.must_apply_timings) {
>  		this->hw.must_apply_timings = false;
> -		gpmi_nfc_apply_timings(this);
> +		ret = gpmi_nfc_apply_timings(this);
> +		if (ret)
> +			return ret;
>  	}
>  
>  	dev_dbg(this->dev, "%s: %d instructions\n", __func__, op->ninstrs);

Acked-by: Han Xu <han.xu@nxp.com>

> -- 
> Christian Eggers
> Embedded software developer
> 
> Arnold & Richter Cine Technik GmbH & Co. Betriebs KG
> Sitz: Muenchen - Registergericht: Amtsgericht Muenchen - Handelsregisternummer: HRA 57918
> Persoenlich haftender Gesellschafter: Arnold & Richter Cine Technik GmbH
> Sitz: Muenchen - Registergericht: Amtsgericht Muenchen - Handelsregisternummer: HRB 54477
> Geschaeftsfuehrer: Dr. Michael Neuhaeuser; Stephan Schenk; Walter Trauninger; Markus Zeiler
>