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References: <20211104102230.123679-1-srinivas.pandruvada@linux.intel.com>
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From:   "Rafael J. Wysocki" <rafael@kernel.org>
Date:   Thu, 4 Nov 2021 19:50:46 +0100
Message-ID: <CAJZ5v0iACra=Ch3GVUV0AgfsSYyLv7F3VFzsb8i2vN=DTxSQXg@mail.gmail.com>
Subject: Re: [PATCH] cpufreq: intel_pstate: Clear HWP Status during HWP
 Interrupt enable
To:     Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Cc:     "Rafael J. Wysocki" <rafael@kernel.org>,
        Viresh Kumar <viresh.kumar@linaro.org>,
        Linux PM <linux-pm@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Len Brown <lenb@kernel.org>
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On Thu, Nov 4, 2021 at 11:22 AM Srinivas Pandruvada
<srinivas.pandruvada@linux.intel.com> wrote:
>
> It is possible that some performance excursions happened before OS boot
> or enable HWP interrupts. So clear MSR_HWP_STATUS bits when we enable
> HWP interrupt. In this way a next excursion will results in a HWP
> interrupt.
>
> The status bits of MSR_HWP_STATUS must be cleared (0) by software so
> that a new status condition change will cause the hardware to set the
> bit again and issue the notification.
>
> Fixes: 57577c996d73 ("cpufreq: intel_pstate: Process HWP Guaranteed change notification")
> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
> ---
>  drivers/cpufreq/intel_pstate.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c
> index 1e6898dc76b6..54cf21896889 100644
> --- a/drivers/cpufreq/intel_pstate.c
> +++ b/drivers/cpufreq/intel_pstate.c
> @@ -1645,6 +1645,7 @@ static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata)
>
>                 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
>                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01);
> +               wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
>         }
>  }
>
> --

Applied as 5.16-rc material, thanks!