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Nikolaus Schaller" In-Reply-To: Date: Sun, 7 Nov 2021 14:45:37 +0100 Cc: Paul Boddie , Rob Herring , Mark Rutland , Thomas Bogendoerfer , Geert Uytterhoeven , Kees Cook , "Eric W. Biederman" , Miquel Raynal , David Airlie , Daniel Vetter , Neil Armstrong , Robert Foss , Laurent Pinchart , Jernej Skrabec , Ezequiel Garcia , Harry Wentland , Sam Ravnborg , Maxime Ripard , Hans Verkuil , Liam Girdwood , Mark Brown , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-mips , linux-kernel , Discussions about the Letux Kernel , Jon as Karlman , dri-devel Content-Transfer-Encoding: quoted-printable Message-Id: <95D1DE70-DDF4-419B-8F0C-E9A6E0995D1F@goldelico.com> References: <3514743.EH6qe8WxYI@jason> To: Paul Cercueil X-Mailer: Apple Mail (2.3445.104.21) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Paul, > Am 05.10.2021 um 23:52 schrieb Paul Cercueil : >=20 > Hi Paul, >=20 > Le mar., oct. 5 2021 at 23:44:12 +0200, Paul Boddie = a =C3=A9crit : >> On Tuesday, 5 October 2021 22:50:12 CEST Paul Cercueil wrote: >>> Hi Nikolaus & Paul, >>> Le mar., oct. 5 2021 at 14:29:17 +0200, H. Nikolaus Schaller >> a =C3=A9crit : >>> > >>> > diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi >>> > b/arch/mips/boot/dts/ingenic/jz4780.dtsi >>> > index 9e34f433b9b5..c3c18a59c377 100644 >>> > --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi >>> > +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi >>> > @@ -424,6 +424,51 @@ i2c4: i2c@10054000 { >>> > >>> > status =3D "disabled"; >>> > >>> > }; >>> > >>> > + hdmi: hdmi@10180000 { >>> > + compatible =3D "ingenic,jz4780-dw-hdmi"; >>> > + reg =3D <0x10180000 0x8000>; >>> > + reg-io-width =3D <4>; >>> > + >>> > + clocks =3D <&cgu JZ4780_CLK_AHB0>, <&cgu = JZ4780_CLK_HDMI>; >>> > + clock-names =3D "iahb", "isfr"; >>> > + >>> > + assigned-clocks =3D <&cgu JZ4780_CLK_HDMI>; >>> > + assigned-clock-rates =3D <27000000>; >>> Any reason why this is set to 27 MHz? Is it even required? Because = with >>> the current ci20.dts, it won't be clocked at anything but 48 MHz. >> EXCLK will be 48MHz, but the aim is to set the HDMI peripheral clock = to 27MHz, >> which is supposedly required. I vaguely recall a conversation about = whether we >> were doing this right, but I don't recall any conclusion. >=20 > But right now your HDMI clock is 48 MHz and HDMI works. Is it? How did you find out? And have you tried to remove assigned-clocks from jz4780.dtsi? 1. I read back: root@letux:~# cat /sys/kernel/debug/clk/hdmi/clk_rate 26909090 root@letux:~#=20 So for me it seems to be running at ~27 MHz. 2. If I remove the assigned-clocks or assigned-clock-rates from DT the boot process hangs shortly after initializing drm. 3. If I set assigned-clock-rates =3D <48000000>, HDMI also works. I get it read back from /sys/kernel/debug/clk/hdmi/clk_rate of 46736842. 4. Conclusions: * assigned-clocks are required * it does not matter if 27 or 48 MHz * I have no idea which value is more correct * so I'd stay on the safe side of 27 MHz 5. But despite that found, please look into the programming manual section 18.1.2.16. There is an "Import Note: The clock must be between 18M and 27M, it occurs fatal error if exceeding the range. " 6. Therefore I think it *may* work overclocked with 48MHz but is not guaranteed or reliable above 27 MHz. So everything is ok here. >=20 >>> > + >>> > + interrupt-parent =3D <&intc>; >>> > + interrupts =3D <3>; >>> > + >>> > + /* ddc-i2c-bus =3D <&i2c4>; */ >>> > + >>> > + status =3D "disabled"; >>> > + }; >>> > + >>> > + lcdc0: lcdc0@13050000 { >>> > + compatible =3D "ingenic,jz4780-lcd"; >>> > + reg =3D <0x13050000 0x1800>; >>> > + >>> > + clocks =3D <&cgu JZ4780_CLK_TVE>, <&cgu = JZ4780_CLK_LCD0PIXCLK>; >>> > + clock-names =3D "lcd", "lcd_pclk"; >>> > + >>> > + interrupt-parent =3D <&intc>; >>> > + interrupts =3D <31>; >>> > + >>> > + status =3D "disabled"; >>> I think you can keep lcdc0 enabled by default (not lcdc1 though), = since >>> it is highly likely that you'd want that. >> As far as I know, the clock gating for the LCD controllers acts like = a series >> circuit, meaning that they both need to be enabled. Some testing = seemed to >> confirm this. Indeed, I seem to remember only enabling one clock and = not >> getting any output until I figured this weird arrangement out. >=20 > I'm not talking about clocks though, but about LCDC0 and LCDC1. Ah, you mean status =3D "okay"; vs. status =3D "disabled"; Well, IMHO it is common practise to keep SoC subsystems disabled by default (to save power and boot time) unless a board specific DTS = explicitly requests the SoC feature to be active. See for example mmc0, mmc1 or = i2c0..i2c4. All these are disabled in jz4780.dtsi and partially enabled in ci20.dts. Why should lcdc0 be an exception in jz4780.dtsi? BR and thanks, Nikolaus