Received: by 2002:a05:6a10:5bc5:0:0:0:0 with SMTP id os5csp5632186pxb; Sun, 7 Nov 2021 16:49:50 -0800 (PST) X-Google-Smtp-Source: ABdhPJxG8aKAFzAddw6fxF5aJLgTB/GwdCaesz8rvqQZQIo46Al9zcGkZPcMmGDGXCasDZtGUHe0 X-Received: by 2002:a17:906:6b81:: with SMTP id l1mr93508509ejr.479.1636332590345; Sun, 07 Nov 2021 16:49:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1636332590; cv=none; d=google.com; s=arc-20160816; b=XN/na5TMRnlYIjbBtS79+DmK7vfnjgvvI4JYM1c+y9WbELgpeqLpMjHtfj/VvFLbND viBLFttZ7gU3UojTT5A+sl6OxEvJkbnruXxcPALH2Svs085ugDFZyDMV0BVvAMheH9pe EigVJmSM3FRqlBd6jYC/25X8/qc7cBCUv5sgFz94Jy5G+bVLt4Ygse+d2oQ64xIot/A3 jEneH/wyZnQTpgy7ikVq0tmDIzKeCLQBjNSNCmGt6l1mzgJ0Uo6mk2yoWfArKHUoF+a7 UFCOeCmwUwsS7USonMGUEHB0OwaMJRuuAHu7CZH8rz/Kbv+5W2KAISgZ09nnPq5FfdX+ 7ivQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:cc:to:subject:from:date; bh=Fp8jjAbG7BpX7l7tq8nPGKFR4N93HfgovGNradTk1DM=; b=j5t9At649mORpV0J0+MP6WSi43F1fLJCXzTsom3ZkcyPrf0mOyojVTeU9WbhZZvMHu AogOhIZ33vxnGyY6RymovGxitnoJRbh+ng7eAyvWW3NhvykiRKW70zlJt2fcpgbtQVY2 H4Vhh6YBP2aoB6jaQ53+8THWMrRK9WcnG8hfZeooIeJehFxpP+/5M95Oj9iK0xj2FUUM mCqygEXbzIY8n1As+Tsyop0F4pssM4l6E2wCHlIuAILeU7rja8hasgdkKVH+uKgALjEs IT4sSW6ktbF95I9a0PoE2Lw5iysJEav3N+CcHdOc+QtCLoSq17XwLNzLMSWXssZCnmAG oIlw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id go43si16318483ejc.141.2021.11.07.16.49.26; Sun, 07 Nov 2021 16:49:50 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236128AbhKGSqa convert rfc822-to-8bit (ORCPT + 99 others); Sun, 7 Nov 2021 13:46:30 -0500 Received: from aposti.net ([89.234.176.197]:49656 "EHLO aposti.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229713AbhKGSqa (ORCPT ); Sun, 7 Nov 2021 13:46:30 -0500 Date: Sun, 07 Nov 2021 18:43:33 +0000 From: Paul Cercueil Subject: Re: [PATCH 0/3] mtd: Ingenic NAND fix for JZ4740 To: "H. Nikolaus Schaller" Cc: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Harvey Hunt , list@opendingux.net, linux-mtd@lists.infradead.org, linux-kernel , linux-mips , Riccardo Mottola , Discussions about the Letux Kernel , Paul Boddie Message-Id: In-Reply-To: <968356A9-2A88-48B1-B31F-55C22BCE620E@goldelico.com> References: <20211009184952.24591-1-paul@crapouillou.net> <968356A9-2A88-48B1-B31F-55C22BCE620E@goldelico.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Nikolaus, Le dim., nov. 7 2021 at 14:47:43 +0100, H. Nikolaus Schaller a ?crit : > Hi Paul, > >> Am 09.10.2021 um 20:49 schrieb Paul Cercueil : >> >> Hi, >> >> Looks like NAND support has been broken on the JZ4740 SoC for a >> while; > > Yes, I remember someone telling that something was fundamentally > broken > and impossible to be fixed a while ago. You mean MLC NAND, and that's still broken. >> it looks like it comes from the fact that the "hw_oob_first" >> mechanism >> was dropped from the NAND core and moved to the Davinci driver. >> >> It turns out the JZ4740 SoC needs it too; I didn't notice it when >> writing the new ingenic-nand driver (to replace the old jz4740-nand >> driver) most likely because my Device Tree had the "nand-ecc-mode" >> set >> to "hw_oob_first". >> >> I am not very sure about patch [1/3]; to me the original code does >> not >> make sense, and it didn't work out-of-the-box on the JZ4740 without >> it. >> By applying patch [1/3] the function >> nand_read_page_hwecc_oob_first() >> can be reused for the JZ4740 SoC as well. But I did not test patch >> [1/3] >> on Davinci. > > would this also work for jz4780 NAND? The JZ4780 NAND driver does work, but UBI refuses to use the CI20's NAND as it's a MLC. -Paul