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Message-ID: <a2a8cca55604755458a2b5daec59290b239a142a.camel@pengutronix.de>
Subject: Re: [PATCH v3 2/3] phy/rockchip: add naneng combo phy for RK3568
From:   Philipp Zabel <p.zabel@pengutronix.de>
To:     Yifeng Zhao <yifeng.zhao@rock-chips.com>, heiko@sntech.de,
        robh+dt@kernel.org
Cc:     devicetree@vger.kernel.org, vkoul@kernel.org,
        michael.riesch@wolfvision.net, linux-rockchip@lists.infradead.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux-phy@lists.infradead.org, kishon@ti.com, cl@rock-chips.com
Date:   Mon, 08 Nov 2021 10:35:09 +0100
In-Reply-To: <20211025080632.32063-3-yifeng.zhao@rock-chips.com>
References: <20211025080632.32063-1-yifeng.zhao@rock-chips.com>
         <20211025080632.32063-3-yifeng.zhao@rock-chips.com>
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On Mon, 2021-10-25 at 16:06 +0800, Yifeng Zhao wrote:
> This patch implements a combo phy driver for Rockchip SoCs
> with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy,
> sata-phy or sgmii-phy.
> 
> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> ---
> 
> Changes in v3:
> - Using api devm_reset_control_get_optional_exclusive and dev_err_probe

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>

regards
Philipp