Received: by 2002:a05:6a10:5bc5:0:0:0:0 with SMTP id os5csp6192880pxb; Mon, 8 Nov 2021 04:48:02 -0800 (PST) X-Google-Smtp-Source: ABdhPJzo+ptf647FuFJU3BJNamHpHIHBwnlkE7iBlvnZ1GzjSr1Nmjq/t21tipG26Ocjx6fh7uPV X-Received: by 2002:aa7:c1c3:: with SMTP id d3mr84121725edp.254.1636375681755; Mon, 08 Nov 2021 04:48:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1636375681; cv=none; d=google.com; s=arc-20160816; b=zDQxp+KlTgLe/4fGvafWbZtH0fYcStv8lA0oeg6CxSgFfMOkiU8DWgG1NJVSj7F7Mf XUlOI7a16FIYbzdcPYwGGvxHV+lMrOxcctTM3E2oKohOT/2Ppa0egF1U3UHzK3L3IhHM iqUU2sNjXpXpL4mzpc7zs+i4Vou20cPSpW/n1W3Y/f7G0T7MNe1U4jHBsdWOZui7taY4 HFH7lw9yMHkgdQp0A9vYr7qEqew6DxnVh/8M3VEoGIXGahQ2V85yKVwLMiok9W8zoAlY TmUBciNO8ZiauGv1Iri8dzoQ+diUtgHIMFBh1BkOXXO2IUqF+QG/ZKE19UtIisFEpOdX 3DFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=vMyXhQWa7qbZvETcMmeoPbb+YQ0Qh3yiQ4k0x4YQRW8=; b=W77rSf+l0Ts4fx8xK3bgpd4/JoXkq2dN0dEAzFvUqWO2UEx48RRmJupM3jDl1eWYrP PEJKZUM1Ra/C+feKTKFA8Qni+nrdDx5ZRvbwU+mREVu3kDiogxsfQNIa7frBo8qdEovo Eal+z1V5iu0hjzyOY/aaiDi8kuwKTd9U80dY3Y5JjQ9dghypcZR3WxuLT+URLhxroL27 17K3PXC5k3TSsu6ouZU7LzrQzscAGB5OVj/c60qIMMiUXNLVO5dd2AOFUg2VxQ3uS1WR Tp+I2zEN/qJL2kwFV05I4ogHXeGMYxeVB5Pc14ZKtkxzmKYa59JYEsBpspvbIkDdohag iN1w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id qb34si18395501ejc.731.2021.11.08.04.47.38; Mon, 08 Nov 2021 04:48:01 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238501AbhKHJsR (ORCPT + 99 others); Mon, 8 Nov 2021 04:48:17 -0500 Received: from mx.socionext.com ([202.248.49.38]:7219 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238323AbhKHJsF (ORCPT ); Mon, 8 Nov 2021 04:48:05 -0500 Received: from unknown (HELO iyokan2-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 08 Nov 2021 18:45:14 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan2-ex.css.socionext.com (Postfix) with ESMTP id AA933206E701; Mon, 8 Nov 2021 18:45:14 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Mon, 8 Nov 2021 18:45:14 +0900 Received: from yuzu2.css.socionext.com (yuzu2 [172.31.9.57]) by iyokan2.css.socionext.com (Postfix) with ESMTP id 1E164B62AE; Mon, 8 Nov 2021 18:45:14 +0900 (JST) Received: from scorpio.e01.socionext.com (aries.syh.socionext.com [10.213.112.88]) by yuzu2.css.socionext.com (Postfix) with ESMTP id 065CAB6292; Mon, 8 Nov 2021 18:45:14 +0900 (JST) From: Sugaya Taichi To: Rob Herring Cc: Arnd Bergmann , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, orito.takao@socionext.com, sugaya.taichi@socionext.com, Masami Hiramatsu , Jassi Brar Subject: [PATCH 1/3] ARM: dts: milbeaut: add a clock node for M10V Date: Mon, 8 Nov 2021 18:45:11 +0900 Message-Id: <1636364713-21451-2-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1636364713-21451-1-git-send-email-sugaya.taichi@socionext.com> References: <1636364713-21451-1-git-send-email-sugaya.taichi@socionext.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a clock node for the platform of the Milbeaut M10V. Signed-off-by: Sugaya Taichi --- arch/arm/boot/dts/milbeaut-m10v.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi b/arch/arm/boot/dts/milbeaut-m10v.dtsi index aa7c6ca..28aee25 100644 --- a/arch/arm/boot/dts/milbeaut-m10v.dtsi +++ b/arch/arm/boot/dts/milbeaut-m10v.dtsi @@ -65,6 +65,13 @@ <0x1d002000 0x1000>; /* CPU I/f base and size */ }; + clk: clock-ctrl@1d021000 { + compatible = "socionext,milbeaut-m10v-ccu"; + #clock-cells = <1>; + reg = <0x1d021000 0x1000>; + clocks = <&uclk40xi>; + }; + timer@1e000050 { /* 32-bit Reload Timers */ compatible = "socionext,milbeaut-timer"; reg = <0x1e000050 0x20>; -- 2.7.4