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Subject: Re: [PATCH v5 5/7] MIPS: DTS: jz4780: Account for Synopsys HDMI
 driver and LCD controllers
From:   "H. Nikolaus Schaller" <hns@goldelico.com>
In-Reply-To: <6WNB2R.GJ2KT1BB7QOY1@crapouillou.net>
Date:   Tue, 9 Nov 2021 21:42:54 +0100
Cc:     Paul Boddie <paul@boddie.org.uk>, Rob Herring <robh+dt@kernel.org>,
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        Discussions about the Letux Kernel 
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To:     Paul Cercueil <paul@crapouillou.net>
Precedence: bulk


> Am 09.11.2021 um 21:36 schrieb Paul Cercueil <paul@crapouillou.net>:
>=20
> Hi Nikolaus,
>=20
> Le mar., nov. 9 2021 at 21:19:17 +0100, H. Nikolaus Schaller =
<hns@goldelico.com> a =C3=A9crit :
>> Hi Paul,
>>> Am 07.11.2021 um 20:05 schrieb Paul Cercueil <paul@crapouillou.net>:
>>>> 6. Therefore I think it *may* work overclocked with 48MHz
>>>> but is not guaranteed or reliable above 27 MHz.
>>>> So everything is ok here.
>>> One thing though - the "assigned-clocks" and "assigned-clock-rates", =
while it works here, should be moved to the CGU node, to respect the =
YAML schemas.
>> Trying to do this seems to break boot.
>> I can boot up to
>> [    8.312926] dw-hdmi-ingenic 10180000.hdmi: registered DesignWare =
HDMI I2C bus driver
>> and
>> [   11.366899] [drm] Initialized ingenic-drm 1.1.0 20200716 for =
13050000.lcdc0 on minor 0
>> but then the boot process becomes slow and hangs. Last sign of =
activity is
>> [   19.347659] hub 1-0:1.0: USB hub found
>> [   19.353478] hub 1-0:1.0: 1 port detected
>> [   32.321760] wlan0_power: disabling
>> What I did was to just move
>> 		assigned-clocks =3D <&cgu JZ4780_CLK_HDMI>;
>> 		assigned-clock-rates =3D <27000000>;
>> from
>> 	hdmi: hdmi@10180000 {
>> to
>> 	cgu: jz4780-cgu@10000000 {
>> Does this mean the clock is assigned too early or too late?
>> Do you have any suggestions since I don't know the details of CGU.
>=20
> These properties are already set for the CGU node in ci20.dts:

Ah, I didn't look into that. Maybe because I thought adding this should =
stay in jz4780.dtsi to be available for any board making use of it.

So it gets overwritten and is then completely missing.

>=20
> &cgu {
> 	/*
> 	 * Use the 32.768 kHz oscillator as the parent of the RTC for a =
higher
> 	 * precision.
> 	 */
> 	assigned-clocks =3D <&cgu JZ4780_CLK_OTGPHY>, <&cgu =
JZ4780_CLK_RTC>;
> 	assigned-clock-parents =3D <0>, <&cgu JZ4780_CLK_RTCLK>;
> 	assigned-clock-rates =3D <48000000>;
> };
>=20
> So you want to update these properties to add the HDMI clock setting, =
like this:
>=20
> 	assigned-clocks =3D <&cgu JZ4780_CLK_OTGPHY>, <&cgu =
JZ4780_CLK_RTC>, <&cgu JZ4780_CLK_HDMI>;
> 	assigned-clock-parents =3D <0>, <&cgu JZ4780_CLK_RTCLK>;
> 	assigned-clock-rates =3D <48000000>, <0>, <27000000>;

Will give it a try.

I would prefer if it could sit in jz4780.dtsi and ci20.dts would just =
extend it but IMHO this is beyond DTS capabilities.
So we likely have to live with that.

BR and thanks,
Nikolaus