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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Nov 2021 10:18:35.4782 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dd26cec7-92d7-49c0-ec3a-08d9a433748f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT021.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2714 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Export the max_physical_apicid via a helper function since this information is required by AMD SVM AVIC support. Reviewed-by: Tom Lendacky Signed-off-by: Suravee Suthikulpanit --- arch/x86/include/asm/apic.h | 1 + arch/x86/kernel/apic/apic.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 48067af94678..77d9cb2a7e28 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -435,6 +435,7 @@ static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} #endif /* CONFIG_X86_LOCAL_APIC */ extern void apic_ack_irq(struct irq_data *data); +extern u32 apic_get_max_phys_apicid(void); static inline void ack_APIC_irq(void) { diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index b70344bf6600..47653d8c05f2 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2361,6 +2361,12 @@ bool apic_id_is_primary_thread(unsigned int apicid) } #endif +u32 apic_get_max_phys_apicid(void) +{ + return max_physical_apicid; +} +EXPORT_SYMBOL_GPL(apic_get_max_phys_apicid); + /* * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids * and cpuid_to_apicid[] synchronized. -- 2.25.1