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References: <20211103124329.171124-1-tomm.merciai@gmail.com>
In-Reply-To: <20211103124329.171124-1-tomm.merciai@gmail.com>
From:   Adam Ford <aford173@gmail.com>
Date:   Wed, 3 Nov 2021 08:19:34 -0500
Message-ID: <CAHCN7x+MbLJ=JLLJBK1_XpW7CtP5NUqZixB0AHnDg=r83uC2Bw@mail.gmail.com>
Subject: Re: [PATCH] arm64: dts: imx8mm: Add NOC node
To:     Tommaso Merciai <tomm.merciai@gmail.com>
Cc:     Rob Herring <robh+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        NXP Linux Team <linux-imx@nxp.com>,
        Lucas Stach <l.stach@pengutronix.de>,
        Joakim Zhang <qiangqing.zhang@nxp.com>,
        Krzysztof Kozlowski <krzk@kernel.org>,
        Frieder Schrempf <frieder.schrempf@kontron.de>,
        Peng Fan <peng.fan@nxp.com>, Alice Guo <alice.guo@nxp.com>,
        devicetree <devicetree@vger.kernel.org>,
        arm-soc <linux-arm-kernel@lists.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Abel Vesa <abelvesa@kernel.org>
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On Wed, Nov 3, 2021 at 7:43 AM Tommaso Merciai <tomm.merciai@gmail.com> wrote:
>
> Add support for dynamic frequency scaling of the main NOC configuration
> on imx8mm.
>
> References:
>  - i.MX 8M Mini Applications Processor RM, Rev. 3, 11/2020
>  - f18e6d573b80 arm64: dts: imx8mq: Add NOC node
>  - 912b9dacf3f0 arm64: dts: imx8mq: increase NOC clock to 800 MHz
> ---

+ Abel

>  arch/arm64/boot/dts/freescale/imx8mm.dtsi | 25 +++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index c2f3f118f82e..c5f64abcecff 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -719,6 +719,31 @@ pgc_mipi: power-domain@11 {
>                         };
>                 };
>
> +               noc: interconnect@32700000 {
> +                       compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc";
> +                       reg = <0x32700000 0x100000>;
> +                       clocks = <&clk IMX8MM_CLK_NOC>;
> +                       fsl,ddrc = <&ddrc>;
> +                       #interconnect-cells = <1>;
> +                       operating-points-v2 = <&noc_opp_table>;
> +
> +                       noc_opp_table: opp-table {
> +                               compatible = "operating-points-v2";
> +
> +                               opp-133M {
> +                                       opp-hz = /bits/ 64 <133333333>;
> +                               };
> +
> +                               opp-400M {
> +                                       opp-hz = /bits/ 64 <400000000>;
> +                               };
> +
> +                               opp-800M {
> +                                       opp-hz = /bits/ 64 <800000000>;
> +                               };

When I look at the opp table from the NXP's custom kernel [1] , they
have a different opp table with a max frequency of 750MHz instead of
800MHz.  The i.MX8MM Ref manual shows there is something at 3270_0000,
but it doesn't go into details of the registers there. However the max
speed of the NOC clock does appear to be 800MHz and not the 750 MHz
listed in the NXP kernel.

However, In the clk node of imx8mm.dtsi file, the IMX8MM_CLK_NOC
parent is set to IMX8MM_SYS_PLL3_OUT and IMX8MM_SYS_PLL3_OUT is set to
750MHz, so I think setting the IMX8MM_CLK_NOC to 800MHz is likely not
what we want if we're setting this clock parent and clock rate to
750MHz.  However if the NOC operates correctly at 800MHz when the
parent is set to IMX8MM_SYS_PLL1_800M, it might make sense.  Looking
at the imx8mq.dtsi file, it appears that the NOC node is referencing
the ddrc node, and the imx8mq is able to operate the ddrc at 800MHz,
while I beleive the 8MM is capped at 750M.

Since I do not know if the NOC is tied to the processor speed, the
DRAM speed, or it runs independently, I can't say with any confidence
what it should be and/or how to test it, but I would assume that with
the ddrc node capped at 750MHz, the opp table in the NXP kernel is
probably the correct one.

[1] - https://source.codeaurora.org/external/imx/linux-imx/tree/arch/arm64/boot/dts/freescale/imx8mm.dtsi?h=lf-5.10.y

adam

> +                       };
> +               };
> +
>                 aips2: bus@30400000 {
>                         compatible = "fsl,aips-bus", "simple-bus";
>                         reg = <0x30400000 0x400000>;
> --
> 2.25.1
>