Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3E97C433EF for ; Wed, 10 Nov 2021 16:38:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9A84461246 for ; Wed, 10 Nov 2021 16:38:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231414AbhKJQlT (ORCPT ); Wed, 10 Nov 2021 11:41:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229582AbhKJQlR (ORCPT ); Wed, 10 Nov 2021 11:41:17 -0500 Received: from mail-ot1-x32b.google.com (mail-ot1-x32b.google.com [IPv6:2607:f8b0:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 368F4C061764 for ; Wed, 10 Nov 2021 08:38:30 -0800 (PST) Received: by mail-ot1-x32b.google.com with SMTP id u18-20020a9d7212000000b00560cb1dc10bso4713309otj.11 for ; Wed, 10 Nov 2021 08:38:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=8O7Ml++eH7v9/z2actv39rMvzGZ2e5JQKOxsiMZkTw8=; b=QrM7VQvAnnZJ+TvjkxLiZWGPxMIb6hTI8O6pku+JNbhr+GNHksX50FBzWCL1NcPRrr ydiJVDCElnod0CfXF2MmbbFg5JO2BXRZBCH14a/m5izYRxI8ohrc44PuyhY7I383RMWt DqjUlJPcD1KmcXUx+uSc4ioHT5lmNYExE5E6Oi95EgoFBSfsdWvHoT7Syq138NPWdFdm zfm/hQk7HxfTd237Z/PAW2EeQVH3NT0S0dtcZkrxVurbweYQwrNTT/5T4s7NpPbkWOL1 zA/qePUjm60vNWz/y1vrd2rcQcSY3QmexqZBO+KwlB5bMib1W5IJdDnoj5t2U3X1RpfB WQNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=8O7Ml++eH7v9/z2actv39rMvzGZ2e5JQKOxsiMZkTw8=; b=GJqfohNo+ih7Qk9YVH/lfS0ZrKCYxL7mJC3uKivq7blLuWNdRgte8/1UVy42XAxZEq 15abp2/BSKAsi6W5afbNJBdvxq6JhPVBi372oUG1cMfV8om8+5cgu0F3QDlQ4D3w0Pz3 5dUSyU0O4yjQ3R39Q9SojdqaXXzcNdH84jhverxAxhfqbkXei/qb4jabk0rmeWOaIfj7 EbVk6kepNGLzF54OGtt+7jyxltorfAUshKy0VVgz8y0SRUkGWPy6is9e0tOcYssH4OLQ SG+T8lfgO4JaJ4bMY/9cXTULTC2tIZKQwp8BynVg8l6T6ktBRzm4uOL9xPMDeg71rUd2 ULAw== X-Gm-Message-State: AOAM533LAysMQm1QZOkGs+WXOd1gX9D/ETqPSUDxU3r1Ahq4tC+TQTJk BGyNGZF5Z5lR7JFzQMGenP5q+7fJUjSKFBzckYIhNhmc X-Google-Smtp-Source: ABdhPJx1W5gm5rRuISODGf7o+AkWxNCzJKvkNJD+nfmrH51sWHNEB4hodQX5h1cBPs9UGfyTt5Kb+f3snNFQM3W6aL4= X-Received: by 2002:a9d:6855:: with SMTP id c21mr432308oto.357.1636562309606; Wed, 10 Nov 2021 08:38:29 -0800 (PST) MIME-Version: 1.0 References: <20211110055303.136782-1-ran.jianping@zte.com.cn> In-Reply-To: <20211110055303.136782-1-ran.jianping@zte.com.cn> From: Alex Deucher Date: Wed, 10 Nov 2021 11:38:18 -0500 Message-ID: Subject: Re: [PATCH] drm/amdgpu: remove unneeded variable To: CGEL Cc: "Quan, Evan" , "Lazar, Lijo" , Chengming Gui , Dave Airlie , Zeal Robot , xinhui pan , LKML , amd-gfx list , "Tuikov, Luben" , Maling list - DRI developers , "Deucher, Alexander" , ran jianping , Kenneth Feng , Christian Koenig Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Applied. Thanks! Alex On Wed, Nov 10, 2021 at 12:53 AM wrote: > > From: ran jianping > > Fix the following coccicheck review: > ./drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c:1174:14-18 > :Unneeded variable > > Remove unneeded variable used to store return value. > > Reported-by: Zeal Robot > Signed-off-by: ran jianping > --- > drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > index a4108025fe29..b0bb389185d5 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c > @@ -1171,7 +1171,7 @@ static int sienna_cichlid_force_clk_levels(struct smu_context *smu, > enum smu_clk_type clk_type, uint32_t mask) > { > struct amdgpu_device *adev = smu->adev; > - int ret = 0, size = 0; > + int ret = 0; > uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; > > soft_min_level = mask ? (ffs(mask) - 1) : 0; > @@ -1216,7 +1216,7 @@ static int sienna_cichlid_force_clk_levels(struct smu_context *smu, > if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK)) > amdgpu_gfx_off_ctrl(adev, true); > > - return size; > + return 0; > } > > static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu) > -- > 2.25.1 >