Message-ID: <45A2AED3.8070609@nortel.com>
Date: Mon, 08 Jan 2007 14:51:31 -0600
From: "Chris Friesen" <cfriesen@nortel.com>
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To: Jan Engelhardt <jengelh@linux01.gwdg.de>
CC: dean gaudet <dean@arctic.org>, "H. Peter Anvin" <hpa@zytor.com>,
       akpm@osdl.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] All Transmeta CPUs have constant TSCs
References: <200701050148.l051mHGM005275@terminus.zytor.com> <Pine.LNX.4.61.0701051524440.7813@yvahk01.tjqt.qr> <Pine.LNX.4.64.0701072358010.26307@twinlark.arctic.org> <Pine.LNX.4.61.0701082118370.23737@yvahk01.tjqt.qr>
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Jan Engelhardt wrote:
> On Jan 8 2007 00:02, dean gaudet wrote:

>>transmeta decided years before intel and amd that a constant rate tsc 
>>(unaffected by P-state) was the only sane choice.  on transmeta cpus the 
>>tsc increments at the maximum cpu frequency no matter what the P-state 
>>(and no matter what longrun is doing behind the kernel's back).

> Well it defeats the purpose of TSC. I mean, they could have kept the "TSC" and
> instead added a second TSC ticker, constant_tsc.

Given that the name is "time stamp counter" then it makes sense to me to 
have a constant frequency.

For performance monitoring it would be useful to have a "cpu cycle 
counter" that counts clock cycles, and varies (and possibly stops) with 
the cpu itself.

Chris


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