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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?6n30h7O3fQEVwKbsjuwmpXfePAj8uulT1zQV2VARA4TTY/ZvTAjEaffUvRzD?= =?us-ascii?Q?Rhy9oyOey+24aG23FG3M1u80n8WzYwojRVP6yCClnae36F2iGsFcEsBDsgWe?= =?us-ascii?Q?mO2jnVBLYf1t5YnOovxcuE4vojp/qIUlDak1bRf2ufn3e0dfUuCXdMKacg2f?= =?us-ascii?Q?YsJtk40cX0T1Ts4l5JbojtM79aWy3YqUy9FI5h35ZNHz1bp+jFsfmrcWAZGN?= =?us-ascii?Q?QHxFrhST9ZaRakTNpsviCf9JIM5/ZEIBO1jnkt5n1hyh1S1Ow6pPn1JRwcj4?= =?us-ascii?Q?D4P90wzwmkPzZgMaWZwX5FFZpXFse4ck2fvxaR82zBcqZy50r4k70ScGY38n?= =?us-ascii?Q?yrX16p0wP2ZFGAdnkj8PPYVl8Kyf1Ccfni6QD2VV7S5ns4azQt3yFPhxtKhf?= =?us-ascii?Q?7BpHXrLmLPxdArGwrM6MguUrMoRNzDoZe6MHHDXn5hjH3BiSFGOYR2o+f1pw?= =?us-ascii?Q?NwJ8VHTbt/4px2q61HMAVqKb2gyAn1lLOaMRVMYJ1o/vB77P2HqXrDA7nVN7?= =?us-ascii?Q?bMJjJOUBYV7k4+EQAGjxgu28uYUNzKtHRChZ10yqSc9aPIGmuuHijLMcrJHA?= =?us-ascii?Q?rSLqiMAqgzR30+bsYTSOGGxEhWrwYGWmxPlao7OKzoi3hSGh+6PNW36+wEGG?= =?us-ascii?Q?QzU/bCBqBUONN2doY33U9eh6sroAxB0YJMHRDMJk9CSNENSm55mrPNgJ7+0m?= =?us-ascii?Q?fkAfRdwIf53ffn1gI6xeW6xrMAZ41IpFGh+/NO5Jlf4diALFIk+BcbbwmYwy?= =?us-ascii?Q?5fLVfvpBM/4f+yvFp5D7E3YBZOYOhrqQfn2k/UwRs7yq8ztR7OIlS2x5KKIG?= =?us-ascii?Q?ZMrmzuqjbyvtoduSZlpaVGEUh90zn913z1de2QdAAQwThMe4cS4mRlrRUOs2?= =?us-ascii?Q?7cbQp9cHqZUC0tni1gGHccE2Gp/pOjFf0LSiW/jJfFwFvWgREc9b45jB2zyj?= =?us-ascii?Q?fpaEARRuewQGx3faJEnFkzC+rVyoRYoD7bEWxuA0tiO1i4a0qrFYUlvOMbmk?= =?us-ascii?Q?cd/HaeBv2zswnxcAxrW8zqB1okfhsUP9OG97IMjWI987O9u3ncwSaZ3GDX/n?= =?us-ascii?Q?RDtUIs3i70ZjuJbV5W0P72QDqwQNwfPe4GJChzeg9xFqKC/1/yimA1rYAzFW?= =?us-ascii?Q?bdRDg0gidu+lJ/9vtsMjocqlkb5oTNW2mR+iFo60DRbkiVXhBlgfQaWS72fJ?= =?us-ascii?Q?rDMLVUCEnHoutx8cVw1Ahe0Z6Hi5oCJ6XRAbJhFJPOiA8PHzpfsYXMitjldC?= =?us-ascii?Q?v+qHjRS0+IIGAQgS/VBjzNy18EzKfkXOCgojVB93fpjgjgZUvwXkEz/T2Rwa?= =?us-ascii?Q?++riCsY16OTErXov9T7sSmEzaHWQjXfGa6OKhrUQX3VA3x+aC+aExes61tcP?= =?us-ascii?Q?d3kVEROIHillPBQYoWpvhWxXjQTf1bdueWbxZFXcdOQZvt/3M3luFZZWdInD?= =?us-ascii?Q?NkVd7/VfrlzB9FsYYNq8qfhWP+zW4yfXRENthCukJ6p5VHTa9JE9SdvmbsUd?= =?us-ascii?Q?naQt/O+TgFH/C2Jheozgri5vVx/nXXvOY2xWFFMSABIK+ixogFPBF0w/zj1D?= =?us-ascii?Q?z9u1xeB1ny+Ena7F1BLmd8llWHe1QJE7GTgrnSpQfQj+P+B0kyu9RlBOa4l5?= =?us-ascii?Q?SRK9O1Mc+5dXZGxHzKqexyQ=3D?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 25060465-7fe5-49a2-5f51-08d9a5a573d4 X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9417.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2021 06:27:08.3878 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: FzN/pdUW9oDzbI2wi91zLz06YFu87QN8WsQjPQIgDfhWfIoAsX4R8c9pMzs5qUBIAl/hyBoNcb7ljZf3o4SrQw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR04MB9473 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Peng Fan i.MX8M Family use A53 Cores and has 32KB ICache with 32KB DCache. - Icache is 2-way set associative - Dcache is 4-way set associative - L2cache is 16-way set associative - Line size are 64bytes Except i.MX8MQ has 1MB L2 Cache, others has 512KB L2 Cache. So add the cache info in device tree and let use could see that from /sys/devices/system/cpu/cpu[x]/cache/ Signed-off-by: Peng Fan --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 28 +++++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mn.dtsi | 28 +++++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 28 +++++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mq.dtsi | 28 +++++++++++++++++++++++ 4 files changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index c2f3f118f82e..5b9c2cca9ac4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -65,6 +65,12 @@ A53_0: cpu@0 { clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; nvmem-cells = <&cpu_speed_grade>; @@ -80,6 +86,12 @@ A53_1: cpu@1 { clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -93,6 +105,12 @@ A53_2: cpu@2 { clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -106,6 +124,12 @@ A53_3: cpu@3 { clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MM_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -114,6 +138,10 @@ A53_3: cpu@3 { A53_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index da6c942fb7f9..ba23b416b5e6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -63,6 +63,12 @@ A53_0: cpu@0 { clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; nvmem-cells = <&cpu_speed_grade>; @@ -78,6 +84,12 @@ A53_1: cpu@1 { clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -91,6 +103,12 @@ A53_2: cpu@2 { clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -104,6 +122,12 @@ A53_3: cpu@3 { clock-latency = <61036>; clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; cpu-idle-states = <&cpu_pd_wait>; @@ -112,6 +136,10 @@ A53_3: cpu@3 { A53_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 04d259de5667..977783784342 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -51,6 +51,12 @@ A53_0: cpu@0 { clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; #cooling-cells = <2>; }; @@ -62,6 +68,12 @@ A53_1: cpu@1 { clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; #cooling-cells = <2>; }; @@ -73,6 +85,12 @@ A53_2: cpu@2 { clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; #cooling-cells = <2>; }; @@ -84,12 +102,22 @@ A53_3: cpu@3 { clock-latency = <61036>; clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; #cooling-cells = <2>; }; A53_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 972766b67a15..95d8b95d6120 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -102,6 +102,12 @@ A53_0: cpu@0 { clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; @@ -116,6 +122,12 @@ A53_1: cpu@1 { clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; @@ -128,6 +140,12 @@ A53_2: cpu@2 { clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; @@ -140,6 +158,12 @@ A53_3: cpu@3 { clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; @@ -147,6 +171,10 @@ A53_3: cpu@3 { A53_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; }; }; -- 2.25.1