From:   Mark Brown <broonie@kernel.org>
To:     Dinh Nguyen <dinguyen@kernel.org>
Cc:     a-nandan@ti.com, linux-spi@vger.kernel.org,
        linux-kernel@vger.kernel.org
In-Reply-To: <20211108200854.3616121-1-dinguyen@kernel.org>
References: <20211108200854.3616121-1-dinguyen@kernel.org>
Subject: Re: [PATCH] spi: cadence-quadspi: fix write completion support
Message-Id: <163675245484.742446.14041471157109637944.b4-ty@kernel.org>
Date:   Fri, 12 Nov 2021 21:27:34 +0000
MIME-Version: 1.0
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Precedence: bulk

On Mon, 8 Nov 2021 14:08:54 -0600, Dinh Nguyen wrote:
> Some versions of the Cadence QSPI controller does not have the write
> completion register implemented(CQSPI_REG_WR_COMPLETION_CTRL). On the
> Intel SoCFPGA platform the CQSPI_REG_WR_COMPLETION_CTRL register is
> not configured.
> 
> Add a quirk to not write to the CQSPI_REG_WR_COMPLETION_CTRL register.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-linus

Thanks!

[1/1] spi: cadence-quadspi: fix write completion support
      commit: 98d948eb833104a094517401ed8be26ba3ce9935

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark