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Mon, 15 Nov 2021 02:19:48 +0000 Received: from PH0PR11MB5191.namprd11.prod.outlook.com ([fe80::a090:40db:80ae:f06a]) by PH0PR11MB5191.namprd11.prod.outlook.com ([fe80::a090:40db:80ae:f06a%9]) with mapi id 15.20.4690.027; Mon, 15 Nov 2021 02:19:48 +0000 From: "Li, Meng" To: "shawnguo@kernel.org" , "leoyang.li@nxp.com" , "robh+dt@kernel.org" CC: "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" Subject: RE: [PATCH] arch: arm64: dts: add delay between CS and CLK signal for flash device Thread-Topic: [PATCH] arch: arm64: dts: add delay between CS and CLK signal for flash device Thread-Index: AQHX0GRWh0F5UroaoU6nw30jLZ/2zKwD7Z+g Date: Mon, 15 Nov 2021 02:19:48 +0000 Message-ID: References: <20211103033838.16015-1-Meng.Li@windriver.com> In-Reply-To: <20211103033838.16015-1-Meng.Li@windriver.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: b35dd384-8eda-4c79-b15e-08d9a7de65c6 x-ms-traffictypediagnostic: PH0PR11MB5109: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:639; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: windriver.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR11MB5191.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: b35dd384-8eda-4c79-b15e-08d9a7de65c6 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Nov 2021 02:19:48.0340 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 8ddb2873-a1ad-4a18-ae4e-4644631433be X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: qhdGGepdlpWlvOq7cOqYLzz3j6KlSnbAK5ZJ+qmDNqgmTNV9tpOI6A/2UQIO7D2hnReow/StYsqtwppzm5KbTA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR11MB5109 X-Proofpoint-GUID: 8TvEGEjZ19Hc_i9qF2HYeTM5b2Tf0rqB X-Proofpoint-ORIG-GUID: 8TvEGEjZ19Hc_i9qF2HYeTM5b2Tf0rqB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-15_01,2021-11-12_01,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 malwarescore=0 mlxlogscore=999 spamscore=0 impostorscore=0 adultscore=0 phishscore=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2111150013 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Is there any comments about this patch? Thanks, Limeng > -----Original Message----- > From: Li, Meng > Sent: Wednesday, November 3, 2021 11:39 AM > To: shawnguo@kernel.org; leoyang.li@nxp.com; robh+dt@kernel.org > Cc: linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > devicetree@vger.kernel.org; Li, Meng > Subject: [PATCH] arch: arm64: dts: add delay between CS and CLK signal fo= r > flash device >=20 > Based on commit d59c90a2400f("spi: spi-fsl-dspi: Convert TCFQ users to XS= PI > FIFO mode ") and 6c1c26ecd9a3("spi: > spi-fsl-dspi: Accelerate transfers using larger word size if possible"), = on > ls1043a-rdb platform, the spi work mode is changed from TCFQ mode to XSPI > mode. In order to keep the transmission sequence matches with flash devic= e, > it is need to add delay between CS and CLK signal. > The strategy of generating delay value refers to QorIQ LS1043A Reference > Manual. >=20 > Signed-off-by: Meng Li > --- > arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 2 ++ > 1 file changed, 2 insertions(+) >=20 > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts > b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts > index 3a669238a0b8..3b1a31a063c6 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts > @@ -98,6 +98,8 @@ > compatible =3D "n25q128a13", "jedec,spi-nor"; /* 16MB */ > reg =3D <0>; > spi-max-frequency =3D <1000000>; /* input clock */ > + fsl,spi-cs-sck-delay =3D <100>; > + fsl,spi-sck-cs-delay =3D <100>; > }; >=20 > slic@2 { > -- > 2.17.1