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Miller" , Sasha Levin Subject: Re: [PATCH 5.4 169/355] net: dsa: lantiq_gswip: serialize access to the PCE table Thread-Topic: [PATCH 5.4 169/355] net: dsa: lantiq_gswip: serialize access to the PCE table Thread-Index: AQHX2kSnOkmxsoPWP0Cc60mbFnJbHqwFPqgA Date: Mon, 15 Nov 2021 23:36:23 +0000 Message-ID: <20211115233622.qdsnq72hlusszzxr@skbuf> References: <20211115165313.549179499@linuxfoundation.org> <20211115165319.255917034@linuxfoundation.org> In-Reply-To: <20211115165319.255917034@linuxfoundation.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 960af84b-518e-4070-b023-08d9a890bc0a x-ms-traffictypediagnostic: VI1PR04MB5696: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:1443; x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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charset="us-ascii" Content-ID: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5136.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 960af84b-518e-4070-b023-08d9a890bc0a X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Nov 2021 23:36:23.2150 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: PGV/6NPjYJa4sUWQ+W7I9Ey3I1dtJuj3IlbZKLy4ivLkdU2rTS2DqhVug1SwXHtk0pL1xLTsjsY+H7Xj7n+Rnw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB5696 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Nov 15, 2021 at 06:01:33PM +0100, Greg Kroah-Hartman wrote: > From: Vladimir Oltean >=20 > [ Upstream commit 49753a75b9a32de4c0393bb8d1e51ea223fda8e4 ] >=20 > Looking at the code, the GSWIP switch appears to hold bridging service > structures (VLANs, FDBs, forwarding rules) in PCE table entries. > Hardware access to the PCE table is non-atomic, and is comprised of > several register reads and writes. >=20 > These accesses are currently serialized by the rtnl_lock, but DSA is > changing its driver API and that lock will no longer be held when > calling ->port_fdb_add() and ->port_fdb_del(). >=20 > So this driver needs to serialize the access to the PCE table using its > own locking scheme. This patch adds that. >=20 > Signed-off-by: Vladimir Oltean > Reviewed-by: Florian Fainelli > Acked-by: Hauke Mehrtens > Signed-off-by: David S. Miller > Signed-off-by: Sasha Levin > --- > drivers/net/dsa/lantiq_gswip.c | 28 +++++++++++++++++++++++----- > 1 file changed, 23 insertions(+), 5 deletions(-) >=20 > diff --git a/drivers/net/dsa/lantiq_gswip.c b/drivers/net/dsa/lantiq_gswi= p.c > index 60e36f46f8abe..d612ef8648baa 100644 > --- a/drivers/net/dsa/lantiq_gswip.c > +++ b/drivers/net/dsa/lantiq_gswip.c > @@ -274,6 +274,7 @@ struct gswip_priv { > int num_gphy_fw; > struct gswip_gphy_fw *gphy_fw; > u32 port_vlan_filter; > + struct mutex pce_table_lock; > }; > =20 > struct gswip_pce_table_entry { > @@ -521,10 +522,14 @@ static int gswip_pce_table_entry_read(struct gswip_= priv *priv, > u16 addr_mode =3D tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD : > GSWIP_PCE_TBL_CTRL_OPMOD_ADRD; > =20 > + mutex_lock(&priv->pce_table_lock); > + > err =3D gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, > GSWIP_PCE_TBL_CTRL_BAS); > - if (err) > + if (err) { > + mutex_unlock(&priv->pce_table_lock); > return err; > + } > =20 > gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); > gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | > @@ -534,8 +539,10 @@ static int gswip_pce_table_entry_read(struct gswip_p= riv *priv, > =20 > err =3D gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, > GSWIP_PCE_TBL_CTRL_BAS); > - if (err) > + if (err) { > + mutex_unlock(&priv->pce_table_lock); > return err; > + } > =20 > for (i =3D 0; i < ARRAY_SIZE(tbl->key); i++) > tbl->key[i] =3D gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i)); > @@ -551,6 +558,8 @@ static int gswip_pce_table_entry_read(struct gswip_pr= iv *priv, > tbl->valid =3D !!(crtl & GSWIP_PCE_TBL_CTRL_VLD); > tbl->gmap =3D (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7; > =20 > + mutex_unlock(&priv->pce_table_lock); > + > return 0; > } > =20 > @@ -563,10 +572,14 @@ static int gswip_pce_table_entry_write(struct gswip= _priv *priv, > u16 addr_mode =3D tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR : > GSWIP_PCE_TBL_CTRL_OPMOD_ADWR; > =20 > + mutex_lock(&priv->pce_table_lock); > + > err =3D gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, > GSWIP_PCE_TBL_CTRL_BAS); > - if (err) > + if (err) { > + mutex_unlock(&priv->pce_table_lock); > return err; > + } > =20 > gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); > gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | > @@ -598,8 +611,12 @@ static int gswip_pce_table_entry_write(struct gswip_= priv *priv, > crtl |=3D GSWIP_PCE_TBL_CTRL_BAS; > gswip_switch_w(priv, crtl, GSWIP_PCE_TBL_CTRL); > =20 > - return gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, > - GSWIP_PCE_TBL_CTRL_BAS); > + err =3D gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, > + GSWIP_PCE_TBL_CTRL_BAS); > + > + mutex_unlock(&priv->pce_table_lock); > + > + return err; > } > =20 > /* Add the LAN port into a bridge with the CPU port by > @@ -2020,6 +2037,7 @@ static int gswip_probe(struct platform_device *pdev= ) > priv->ds->priv =3D priv; > priv->ds->ops =3D &gswip_switch_ops; > priv->dev =3D dev; > + mutex_init(&priv->pce_table_lock); > version =3D gswip_switch_r(priv, GSWIP_VERSION); > =20 > /* bring up the mdio bus */ > --=20 > 2.33.0 >=20 >=20 > As discussed on the v5.14 backport, this patch can be dropped. Same thing for the 5.10 version of the backport.=