Message-ID: <9ee9584833d948188347414991a117ca86edfaaf.camel@gmail.com>
Subject: Re: [PATCH v3 2/2] i2c: exynos5: add support for ExynosAutov9 SoC
From:   David Virag <virag.david003@gmail.com>
To:     Chanho Park <chanho61.park@samsung.com>,
        'Sam Protsenko' <semen.protsenko@linaro.org>,
        'Jaewon Kim' <jaewon02.kim@samsung.com>
Cc:     'Krzysztof Kozlowski' <krzysztof.kozlowski@canonical.com>,
        'Wolfram Sang' <wsa@kernel.org>,
        'Rob Herring' <robh+dt@kernel.org>,
        linux-samsung-soc@vger.kernel.org, linux-i2c@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org
Date:   Wed, 17 Nov 2021 23:17:55 +0100
In-Reply-To: <001401d7da86$f7ebd660$e7c38320$@samsung.com>
References: <CGME20211112010603epcas2p339d1a6ef3df7cdbe61c87c8afa541fd0@epcas2p3.samsung.com>
         <20211112010137.149174-1-jaewon02.kim@samsung.com>
         <20211112010137.149174-3-jaewon02.kim@samsung.com>
         <CAPLW+4==X+irRBKHiDfgJeAb0oDKkzbcWERFs7Y3=PSOg0+qAw@mail.gmail.com>
         <001401d7da86$f7ebd660$e7c38320$@samsung.com>
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> Current version of USI is v2 which means there is a v1 version as well.
> It might be a non-upstream SoC so we don't need to consider it so far.

The Exynos7885 I'm working on has USI v1. It doesn't seem to be heavily
used as the SoC has just 3 USI blocks if I didn't miss anything.

The most obvious difference I saw was instead of having 3 modes (SPI,
UART, and HSI2C) It has:
 - SPI
 - HSI2C0 (meaning I2C pins are connected to the first 2 pins out of
the 4 if I understand it correctly)
 - HSI2C1 (connected to last 2 pins)
 - HSI2C0_HSI2C1 (2 I2C devices connected to first 2 and last 2 pins)
 - UART
 - UART_HSI2C1 (first 2 pins are UART, rest is I2C)

Also there doesn't seem to be any USI_CON or USI_OPTION registers in
SPI, UART, or I2C. It seems like it's just the USI driver doing all the
work (just setting up the SYSREG) and the I2C driver writing values to
the SYSREG at suspend/resume for some reason. 

From the looks of it, it doesn't look like it'd be hard to add this to
USI v2 drivers when needed. (USI driver (if that's the way it will go)
would just need minor modifications to add v1 modes and UART/SPI/I2C
drivers may just work with non-USI compatibles/would only need SoC
specific data added).

Best Regards,
David