Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3C31C433F5 for ; Fri, 19 Nov 2021 13:31:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D9AE761AF0 for ; Fri, 19 Nov 2021 13:31:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235476AbhKSNeT (ORCPT ); Fri, 19 Nov 2021 08:34:19 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:42620 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235458AbhKSNeQ (ORCPT ); Fri, 19 Nov 2021 08:34:16 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 1AJDVAYv118524; Fri, 19 Nov 2021 07:31:10 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1637328670; bh=XnOnabdqZpR0cTWt8bf9FmPxCxWw5rQak76g7JRxugo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=yvJFZiH8hRIK+zSU3dXs3PDYKww3PAdywzKw85JvbYSQKnDsARDpA7fNBvTS8B2bg RgkBh+9zwdPyvdGXbthwIQE9eav1yHr5pszLTRq8rq6fUsWO9lFRka0DpCHObCiBJD 8ANnMiySw0ZCb98DR8mdwFAR7jpSVQIztYoz4FBw= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 1AJDV9W2041085 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 19 Nov 2021 07:31:10 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Fri, 19 Nov 2021 07:31:09 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Fri, 19 Nov 2021 07:31:09 -0600 Received: from gsaswath-HP-ProBook-640-G5.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1AJDUrNu123745; Fri, 19 Nov 2021 07:31:07 -0600 From: Aswath Govindraju CC: Nishanth Menon , Vignesh Raghavendra , Kishon Vijay Abraham I , Aswath Govindraju , Tero Kristo , Rob Herring , , , Subject: [PATCH 2/5] dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721S2 Date: Fri, 19 Nov 2021 19:00:47 +0530 Message-ID: <20211119133052.17793-3-a-govindraju@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211119133052.17793-1-a-govindraju@ti.com> References: <20211119133052.17793-1-a-govindraju@ti.com> MIME-Version: 1.0 Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add pinctrl macros for J721S2 SoC. These macro definitions are similar to that of J721E, but adding new definitions to avoid any naming confusions in the soc dts files. checkpatch insists the following error exists: ERROR: Macros with complex values should be enclosed in parentheses However, we do not need parentheses enclosing the values for this macro as we do intend it to generate two separate values as has been done for other similar platforms. Signed-off-by: Aswath Govindraju --- include/dt-bindings/pinctrl/k3.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h index e085f102b283..63e038e36ca3 100644 --- a/include/dt-bindings/pinctrl/k3.h +++ b/include/dt-bindings/pinctrl/k3.h @@ -38,4 +38,7 @@ #define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + #endif -- 2.17.1