Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF7BAC4332F for ; Sun, 21 Nov 2021 23:35:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230325AbhKUXiq (ORCPT ); Sun, 21 Nov 2021 18:38:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45138 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229735AbhKUXio (ORCPT ); Sun, 21 Nov 2021 18:38:44 -0500 Received: from mail-ot1-x336.google.com (mail-ot1-x336.google.com [IPv6:2607:f8b0:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AAEBBC061574 for ; Sun, 21 Nov 2021 15:35:38 -0800 (PST) Received: by mail-ot1-x336.google.com with SMTP id h12-20020a056830034c00b0055c8458126fso26288420ote.0 for ; Sun, 21 Nov 2021 15:35:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=BaBwOZhHd4DxX6OyrXmhy1nl2ZJax3QUSfV+91vGF7M=; b=K+j7e9qBhUAibBOZEuR3+OvgRRz5+9kXuJpfy7hOrCUUI5mVAVvfPjVaSaQWagEtmD VaQjSDZvZCKKfl/PaO0UdwCeIlqMJ7eJooO6eT7GjoXW1uvDDryVqntBnxqhbhpAdjE3 CmxKLcWB9dGg5+uW12IGRoofHXHVRV9TegwAW6qUaX/HiDYCvGQYSP2/TGLWo1eJk41q HLONx6bHVQumcQ5Vy4Z+6fD/ZgNYF7VwvELj9YticGsmN4Q2lcnFiWT5fPI5W1ugXnAY wRaew207TxZ9kuepimcJjzsp7th6vntEkiki7IDzihCyEVwhCSWDlcpKyzXN5bcdu5J+ tDSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=BaBwOZhHd4DxX6OyrXmhy1nl2ZJax3QUSfV+91vGF7M=; b=q/AlMXr3F9Kaa1jDukCh+QOiR+yZ9ZjoR/olFuTaCTg1plDeC/uWH7s/n2Ens/qaLE 9OFohKFwNLaJoBFdEoZBRM0eVuxeTMOC/P4q8td/IYRGu4NvKC1MVimumLYa6iq/VlC+ vSSKA9GZ4aBgNoTQSMbHwu10XrjOYxcXx465xh/3cQP+JYt+AgNInMdq4jKEXgksegbf IlaLr6eOGUhNHdscbfTNZ4rXH5uFlXexfpkxMsE9PyVGE8HYw9hz1giTK4n93vwLP3mS QgmFrNN9Akr+N1SZu3z5pTDGk4IH1PAXifWVwHJsDZQkiKBZmnnjaBrE5IlVQ6pdCcSC Xz9g== X-Gm-Message-State: AOAM530IoX8tkf2eas6tV3vA81nEfKLyK7tnv9Qx9TcQvOXkHisVeVUB vW+q5yWgGm6Tt+RK9BlFCX3WdUb6r6adZHe7GNF9FA== X-Google-Smtp-Source: ABdhPJxP1hm4dAk3hP5iwxGTmVS5kCY5d1BVX1iWfJPo1f0KYbx3q9C2qhLGJ7JQjety/S6BZHEqWcsnr8krInQwy+4= X-Received: by 2002:a9d:a42:: with SMTP id 60mr21475101otg.179.1637537737964; Sun, 21 Nov 2021 15:35:37 -0800 (PST) MIME-Version: 1.0 References: <20211116150119.2171-1-kernel@esmil.dk> <20211116150119.2171-13-kernel@esmil.dk> In-Reply-To: <20211116150119.2171-13-kernel@esmil.dk> From: Linus Walleij Date: Mon, 22 Nov 2021 00:35:26 +0100 Message-ID: Subject: Re: [PATCH v4 12/16] pinctrl: starfive: Add pinctrl driver for StarFive SoCs To: Emil Renner Berthing Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Rob Herring , Michael Turquette , Stephen Boyd , Thomas Gleixner , Marc Zyngier , Philipp Zabel , Greg Kroah-Hartman , Daniel Lezcano , Andy Shevchenko , Jiri Slaby , Maximilian Luz , Sagar Kadam , Drew Fustini , Geert Uytterhoeven , Michael Zhu , Fu Wei , Anup Patel , Atish Patra , Matteo Croce , Arnd Bergmann , linux-kernel@vger.kernel.org, Huan Feng Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Nov 16, 2021 at 4:02 PM Emil Renner Berthing wrote: > Add a combined pinctrl and GPIO driver for the JH7100 RISC-V SoC by > StarFive Ltd. This is a test chip for their upcoming JH7110 SoC, which > is said to feature only minor changes to these pinctrl/GPIO parts. > > For each "GPIO" there are two registers for configuring the output and > output enable signals which may come from other peripherals. Among these > are two special signals that are constant 0 and constant 1 respectively. > Controlling the GPIOs from software is done by choosing one of these > signals. In other words the same registers are used for both pin muxing > and controlling the GPIOs, which makes it easier to combine the pinctrl > and GPIO driver in one. > > I wrote the pinconf and pinmux parts, but the GPIO part of the code is > based on the GPIO driver in the vendor tree written by Huan Feng with > cleanups and fixes by Drew and me. > > Datasheet: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf > Co-developed-by: Huan Feng > Signed-off-by: Huan Feng > Signed-off-by: Emil Renner Berthing > Co-developed-by: Drew Fustini > Signed-off-by: Drew Fustini Overall there is nothing wrong with this, and it is in nice shape. Let's merge it: Reviewed-by: Linus Walleij Yours, Linus Walleij