Message-ID: <68544192-0c4f-ed64-27a2-0bfe2d7805b5@kernel.org>
Date:   Mon, 22 Nov 2021 17:25:27 +0200
MIME-Version: 1.0
Subject: Re: [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect
 provider
Content-Language: en-US
To:     bjorn.andersson@linaro.org,
        Odelu Kukatla <okukatla@codeaurora.org>,
        georgi.djakov@linaro.org, evgreen@google.com,
        Andy Gross <agross@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
Cc:     sboyd@kernel.org, mdtipton@codeaurora.org, sibis@codeaurora.org,
        saravanak@google.com, seansw@qti.qualcomm.com, elder@linaro.org,
        linux-pm@vger.kernel.org, linux-arm-msm-owner@vger.kernel.org
References: <1634812857-10676-1-git-send-email-okukatla@codeaurora.org>
 <1634812857-10676-4-git-send-email-okukatla@codeaurora.org>
From:   Georgi Djakov <djakov@kernel.org>
In-Reply-To: <1634812857-10676-4-git-send-email-okukatla@codeaurora.org>
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Precedence: bulk

On 21.10.21 13:40, Odelu Kukatla wrote:
> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
> SoCs.
> 
> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>

Acked-by: Georgi Djakov <djakov@kernel.org>

> ---
>   arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++
>   1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index d74a4c8..0b55742 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -3687,6 +3687,14 @@
>   			};
>   		};
>   
> +		epss_l3: interconnect@18590000 {
> +			compatible = "qcom,sc7280-epss-l3";
> +			reg = <0 0x18590000 0 0x1000>;
> +			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
> +			clock-names = "xo", "alternate";
> +			#interconnect-cells = <1>;
> +		};
> +
>   		cpufreq_hw: cpufreq@18591000 {
>   			compatible = "qcom,cpufreq-epss";
>   			reg = <0 0x18591000 0 0x1000>,
>