From:   Heiko =?ISO-8859-1?Q?St=FCbner?= <heiko@sntech.de>
To:     linus.walleij@linaro.org, bgolaszewski@baylibre.com,
        robh+dt@kernel.org, jassisinghbrar@gmail.com,
        paul.walmsley@sifive.com, palmer@dabbelt.com,
        aou@eecs.berkeley.edu, a.zummo@towertech.it,
        alexandre.belloni@bootlin.com, broonie@kernel.org,
        gregkh@linuxfoundation.org, lewis.hanly@microchip.com,
        conor.dooley@microchip.com, daire.mcnamara@microchip.com,
        atish.patra@wdc.com, ivan.griffin@microchip.com,
        linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org,
        linux-riscv@lists.infradead.org, linux-crypto@vger.kernel.org,
        linux-rtc@vger.kernel.org, linux-spi@vger.kernel.org,
        linux-usb@vger.kernel.org
Cc:     krzysztof.kozlowski@canonical.com, geert@linux-m68k.org,
        bin.meng@windriver.com, conor.dooley@microchip.com
Subject: Re: [PATCH 01/13] dt-bindings: interrupt-controller: create a header for RISC-V interrupts
Date:   Tue, 23 Nov 2021 12:07:52 +0100
Message-ID: <272946671.hFph3VMliC@diego>
In-Reply-To: <20211108150554.4457-2-conor.dooley@microchip.com>
References: <20211108150554.4457-1-conor.dooley@microchip.com> <20211108150554.4457-2-conor.dooley@microchip.com>
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Am Montag, 8. November 2021, 16:05:42 CET schrieb conor.dooley@microchip.com:
> From: Ivan Griffin <ivan.griffin@microchip.com>
> 
> Provide named identifiers for device tree for RISC-V interrupts.
> 
> Licensed under GPL and MIT, as this file may be useful to any OS that
> uses device tree.
> 
> Signed-off-by: Ivan Griffin <ivan.griffin@microchip.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  .../interrupt-controller/riscv-hart.h         | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>  create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h
> 
> diff --git a/include/dt-bindings/interrupt-controller/riscv-hart.h b/include/dt-bindings/interrupt-controller/riscv-hart.h
> new file mode 100644
> index 000000000000..e1c32f6090ac
> --- /dev/null
> +++ b/include/dt-bindings/interrupt-controller/riscv-hart.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/*
> + * Copyright (C) 2021 Microchip Technology Inc.  All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H
> +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H
> +
> +#define HART_INT_U_SOFT   0
> +#define HART_INT_S_SOFT   1
> +#define HART_INT_M_SOFT   3
> +#define HART_INT_U_TIMER  4
> +#define HART_INT_S_TIMER  5
> +#define HART_INT_M_TIMER  7
> +#define HART_INT_U_EXT    8
> +#define HART_INT_S_EXT    9
> +#define HART_INT_M_EXT    11

(1) From checking clic doc [0] I see an additional
	12   CLIC software interrupt
defined.

(2) The doc states that the ordering is a recommendation and
	"not mandatory in all incarnations of the CLIC"
Is that clarified somewhere else that this more than recommended?

Thanks
Heiko


[0] https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc

> +
> +#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H */
>