Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7C28C4167D for ; Tue, 23 Nov 2021 11:24:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236096AbhKWL1b (ORCPT ); Tue, 23 Nov 2021 06:27:31 -0500 Received: from gloria.sntech.de ([185.11.138.130]:52222 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234496AbhKWL1a (ORCPT ); Tue, 23 Nov 2021 06:27:30 -0500 Received: from ip5f5b2004.dynamic.kabel-deutschland.de ([95.91.32.4] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mpTuB-0008Cw-Pk; Tue, 23 Nov 2021 12:24:07 +0100 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Conor Dooley , linux-riscv@lists.infradead.org Cc: Linus Walleij , Bartosz Golaszewski , Rob Herring , Jassi Brar , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alessandro Zummo , Alexandre Belloni , Mark Brown , Greg KH , Lewis Hanly , Daire.McNamara@microchip.com, Atish Patra , Ivan.Griffin@microchip.com, "open list:GPIO SUBSYSTEM" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux Kernel Mailing List , Linux I2C , linux-riscv , Linux Crypto Mailing List , linux-rtc@vger.kernel.org, linux-spi , USB list , Krzysztof Kozlowski , Bin Meng , Geert Uytterhoeven Subject: Re: [PATCH 04/13] dt-bindings: riscv: update microchip polarfire binds Date: Tue, 23 Nov 2021 12:24:06 +0100 Message-ID: <2736394.7QafvNDC63@diego> In-Reply-To: References: <20211108150554.4457-1-conor.dooley@microchip.com> <198eaf69-8f85-50a7-192e-5900776d044b@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Dienstag, 9. November 2021, 14:04:45 CET schrieb Geert Uytterhoeven: > Hi Conor, > > On Tue, Nov 9, 2021 at 1:08 PM wrote: > > On 09/11/2021 08:34, Geert Uytterhoeven wrote: > > > On Mon, Nov 8, 2021 at 4:06 PM wrote: > > >> From: Conor Dooley > > >> > > >> Add mpfs-soc to clear undocumented binding warning > > >> > > >> Signed-off-by: Conor Dooley > > > >> --- a/Documentation/devicetree/bindings/riscv/microchip.yaml > > >> +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml > > >> @@ -21,6 +21,7 @@ properties: > > >> - enum: > > >> - microchip,mpfs-icicle-kit > > >> - const: microchip,mpfs > > >> + - const: microchip,mpfs-soc > > > > > > Doesn't the "s" in "mpfs" already stand for "soc"? > > not wrong, but using mpf-soc would be confusing since "mpf" is the part > > name for the non soc fpga. is it fine to just reuse "mpfs" for the dtsi > > overall compatible and for the soc subsection? > > I really meant: what is the difference between "microchip,mpfs" and > "microchip,mpfs-soc"? Can't you just use the former? definitly agreed :-) Having the board named as compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs" sounds the most sensible. As Conor wrote, "mpfs" is the name of the soc itself - with mpf being the fpga part, so that would follow what boards in other parts of the kernel do. Heiko