From:   Sean Anderson <sean.anderson@seco.com>
To:     linux-pwm@vger.kernel.org, devicetree@vger.kernel.org,
        Thierry Reding <thierry.reding@gmail.com>
Cc:     linux-arm-kernel@lists.infradead.org,
        Alvaro Gamez <alvaro.gamez@hazent.com>,
        Lee Jones <lee.jones@linaro.org>,
        =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= 
        <u.kleine-koenig@pengutronix.de>, michal.simek@xilinx.com,
        linux-kernel@vger.kernel.org,
        Sean Anderson <sean.anderson@seco.com>,
        Rob Herring <robh@kernel.org>
Subject: [PATCH v11 1/2] dt-bindings: pwm: Add Xilinx AXI Timer
Date:   Tue, 23 Nov 2021 18:25:35 -0500
Message-Id: <20211123232536.3909773-1-sean.anderson@seco.com>
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?0bdi3kVlFZRqS/jSofIrr6ubsJmcQ0b5kBMEjVUsRMKT9qKDPSU6bey3NR+N?=
 =?us-ascii?Q?DF1S9yaEfiZBxfhDPQeiag1mZbOyU8rid0cZgycMr+g33vXaQeyQ8fGAfyu4?=
 =?us-ascii?Q?EGLE+PCuPe+qFu+zbVR5nGbp3UwTtnrTBDznIiZN/su7JtFctaHZ41ILPZYi?=
 =?us-ascii?Q?nV34WSL26lUVkWsbKaVCNDYRuCMl0K/aV3M1rUyEMgOT3TAW9x9Rw7+t7NVU?=
 =?us-ascii?Q?A0VmBFPg2FB9B8TZAnh0nFAkA2VmK6WirX6EROgcrqaYe4wcEYCWCsxwjGIQ?=
 =?us-ascii?Q?pQxnCFvssyWsKAhjMS8gre9beNFXTSxZJ/6uDq0uiCmXmqJ1WEE88ZM4qBgU?=
 =?us-ascii?Q?bXUP8Pa3Q0Ab61gXAdmsLh466djTwZDMN2oydgGZWwQwkc7dOWjfgr3CPQKt?=
 =?us-ascii?Q?SS3bbIaMhFZ5sydYLlJYEb19zvvc50sYV4qJMQ1b7eAoCLHhK+JzqavmkI8x?=
 =?us-ascii?Q?Ymd/pBNFjnC5bnOk7KIPddQRglUyxaDshS0eljoIHbHNsJdGhsYYCzmsVjK6?=
 =?us-ascii?Q?Ap/dfCVG6PAI3IwWQvAZAA1D1jp9ZBAlpWvoVch4TdHvqUB3440H2e2ghyTt?=
 =?us-ascii?Q?w5/kb1/1z4YeGNE+HiqEVDCjuumO8z+YsA/wIzLQcbqIwOKkv2NI+XM7jh9I?=
 =?us-ascii?Q?RHrNiSB4Yl72CnRjKWmrkM0t3r6B/knj8plTFtkikeRvS6u61T+NkrYWpDwT?=
 =?us-ascii?Q?EMvrZIGUIEXRoQXa0ZX9Z6c8hF3ukuk8it9p4T9VMLPeGbl2JGxx6jvf1MUa?=
 =?us-ascii?Q?3f0+JE2bMWVN+5ADaMrVUUuZZreW4IXpaFlxDupDBQlZWPToQlXrE+ayUlRb?=
 =?us-ascii?Q?JV2KASmwSY6imbDvQuPsEvoONIIC4UN0Z1BFtORnORMD5xM8ngFKuQpUXm7P?=
 =?us-ascii?Q?MXA6hwAkzKhLpsjrndcVdj/RVpeuwua7LIxnU504e+jh5XMbDPQ8pfHmdMTk?=
 =?us-ascii?Q?TxUVrWScPomb8tWRf1myOZutqDvxIL2llVI9YLylxtH6yCT5u/xf6P7rFa5x?=
 =?us-ascii?Q?XR1/EJRG5oeOB8KuB3ygdtaZGcBJYfu/DjDXGGlZKC9mKnL3UGjjD9jMXMaj?=
 =?us-ascii?Q?Vf9uOCxBtES6/XRt6eq73jT/M+Ab/YRpEX2IvZkRw2MvqmGD0WnErbwRBgqB?=
 =?us-ascii?Q?NAat4BNJ6U7+ARvbsW6bZVEa+QGOyL1FauOpXUrcQiIOS8sPyMW1quhlrB96?=
 =?us-ascii?Q?84PFmnl9PSY/75NIWrdY4gyuXn1ZmDSto66PFqLKFLXwaVTsfe+a9NFoo7RS?=
 =?us-ascii?Q?1ynjvMjpfbSpQ+VA3a5+PpCKrRuUbgTxCnO5GGwscijVpu6AG+NMoJiRtXR1?=
 =?us-ascii?Q?WrLOB4zilI4DfworHodBE18wrMjBZ2nv2JnAcjtmgwHleoyADFNuKRxyNP4g?=
 =?us-ascii?Q?eMPRVK1l8Je7cwi2MVGwPGx6qZeE0jfJpbQr+estJ+Gvqc6sFDHrJnn3wXJQ?=
 =?us-ascii?Q?4GYdg1cgT3uzApBZdZtj1WHV8yh6NiR4aOl1BNFR9dLaDecll91ELsKSwZp4?=
 =?us-ascii?Q?wUoML5ETvKMmDmzcuxJA1cliSkPHlyVmq9OjM1tEK7uNqFdZYKe2r/m6J0mq?=
 =?us-ascii?Q?ZRp4qbYaav2xaPTJymX4lKSZBZ9C8A+E0cxRYpRUH3JJVwa8eX8j3IGePcpC?=
 =?us-ascii?Q?8q2ukwpb3qCHr4cVUP5Hny4=3D?=
X-OriginatorOrg: seco.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 8befa90d-36dc-4ffd-eeb7-08d9aed89534
X-MS-Exchange-CrossTenant-AuthSource: AM6PR03MB4518.eurprd03.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2021 23:25:49.0238
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: bebe97c3-6438-442e-ade3-ff17aa50e733
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: TW/mLzku0YzZsXLYp0uHKZnhRGM/zmEWdUbLHJs1fN3xtfevTbq3sRJkEc9cxUNOgRgiWigPkwJ1KTo1kpuQLg==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR03MB3942
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is a
"soft" block, so it has some parameters which would not be configurable in
most hardware. This binding is usually automatically generated by Xilinx's
tools, so the names and values of some properties should be kept as they
are, if possible. In addition, this binding is already in the kernel at
arch/microblaze/boot/dts/system.dts, and in user software such as QEMU.

The existing driver uses the clock-frequency property, or alternatively the
/cpus/timebase-frequency property as its frequency input. Because these
properties are deprecated, they have not been included with this schema.
All new bindings should use the clocks/clock-names properties to specify
the parent clock.

Because we need to init timer devices so early in boot, we determine if we
should use the PWM driver or the clocksource/clockevent driver by the
presence/absence, respectively, of #pwm-cells. Because both counters are
used by the PWM, there is no need for a separate property specifying which
counters are to be used for the PWM.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---

(no changes since v8)

Changes in v8:
- Set additionalProperties: false

Changes in v7:
- Add #pwm-cells to properties
- Document why additionalProperties is true

Changes in v6:
- Enumerate possible counter widths
- Fix incorrect schema id

Changes in v5:
- Add example for timer binding
- Fix indentation lint
- Move schema into the timer directory
- Remove xlnx,axi-timer-2.0 compatible string
- Update commit message to reflect revisions

Changes in v4:
- Make some properties optional for clocksource drivers
- Predicate PWM driver on the presence of #pwm-cells
- Remove references to generate polarity so this can get merged

Changes in v3:
- Add an example with non-deprecated properties only.
- Add xlnx,pwm and xlnx,gen?-active-low properties.
- Make newer replacement properties mutually-exclusive with what they
  replace
- Mark all boolean-as-int properties as deprecated

Changes in v2:
- Use 32-bit addresses for example binding

 .../bindings/timer/xlnx,xps-timer.yaml        | 92 +++++++++++++++++++
 1 file changed, 92 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml

diff --git a/Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml b/Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml
new file mode 100644
index 000000000000..dd168d41d2e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/xlnx,xps-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx LogiCORE IP AXI Timer Device Tree Binding
+
+maintainers:
+  - Sean Anderson <sean.anderson@seco.com>
+
+properties:
+  compatible:
+    contains:
+      const: xlnx,xps-timer-1.00.a
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: s_axi_aclk
+
+  interrupts:
+    maxItems: 1
+
+  reg:
+    maxItems: 1
+
+  '#pwm-cells': true
+
+  xlnx,count-width:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [8, 16, 32]
+    default: 32
+    description:
+      The width of the counter(s), in bits.
+
+  xlnx,one-timer-only:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [ 0, 1 ]
+    description:
+      Whether only one timer is present in this block.
+
+required:
+  - compatible
+  - reg
+  - xlnx,one-timer-only
+
+allOf:
+  - if:
+      required:
+        - '#pwm-cells'
+    then:
+      allOf:
+        - required:
+            - clocks
+        - properties:
+            xlnx,one-timer-only:
+              const: 0
+    else:
+      required:
+        - interrupts
+  - if:
+      required:
+        - clocks
+    then:
+      required:
+        - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    timer@800e0000 {
+        clock-names = "s_axi_aclk";
+        clocks = <&zynqmp_clk 71>;
+        compatible = "xlnx,xps-timer-1.00.a";
+        reg = <0x800e0000 0x10000>;
+        interrupts = <0 39 2>;
+        xlnx,count-width = <16>;
+        xlnx,one-timer-only = <0x0>;
+    };
+
+    timer@800f0000 {
+        #pwm-cells = <0>;
+        clock-names = "s_axi_aclk";
+        clocks = <&zynqmp_clk 71>;
+        compatible = "xlnx,xps-timer-1.00.a";
+        reg = <0x800e0000 0x10000>;
+        xlnx,count-width = <32>;
+        xlnx,one-timer-only = <0x0>;
+    };
-- 
2.25.1