Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAD93C4332F for ; Wed, 24 Nov 2021 08:46:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233622AbhKXIt5 (ORCPT ); Wed, 24 Nov 2021 03:49:57 -0500 Received: from mx24.baidu.com ([111.206.215.185]:34066 "EHLO baidu.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233027AbhKXItt (ORCPT ); Wed, 24 Nov 2021 03:49:49 -0500 Received: from BC-Mail-Ex16.internal.baidu.com (unknown [172.31.51.56]) by Forcepoint Email with ESMTPS id A0D5B962179B7B1CA537; Wed, 24 Nov 2021 16:46:35 +0800 (CST) Received: from BJHW-MAIL-EX27.internal.baidu.com (10.127.64.42) by BC-Mail-Ex16.internal.baidu.com (172.31.51.56) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.20; Wed, 24 Nov 2021 16:46:35 +0800 Received: from LAPTOP-UKSR4ENP.internal.baidu.com (172.31.63.8) by BJHW-MAIL-EX27.internal.baidu.com (10.127.64.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.20; Wed, 24 Nov 2021 16:46:34 +0800 From: Cai Huoqing To: CC: Rob Herring , Greg Kroah-Hartman , , , Subject: [PATCH v2 2/3] dt-bindings: staging: Add the binding documentation for ZHOUYI AI accelerator Date: Wed, 24 Nov 2021 16:46:16 +0800 Message-ID: <20211124084620.628-3-caihuoqing@baidu.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211124084620.628-1-caihuoqing@baidu.com> References: <20211124084620.628-1-caihuoqing@baidu.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [172.31.63.8] X-ClientProxiedBy: BC-Mail-Ex25.internal.baidu.com (172.31.51.19) To BJHW-MAIL-EX27.internal.baidu.com (10.127.64.42) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ZHOUYI NPU is an AI accelerator chip which is integrated into ARM SOC, such as Allwinner R329 SOC. Add the binding documentation for ZHOUYI AI accelerator. Signed-off-by: Cai Huoqing --- .../bindings/staging/arm,zynpu.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/staging/arm,zynpu.yaml diff --git a/Documentation/devicetree/bindings/staging/arm,zynpu.yaml b/Documentation/devicetree/bindings/staging/arm,zynpu.yaml new file mode 100644 index 000000000000..d452c08ab4a3 --- /dev/null +++ b/Documentation/devicetree/bindings/staging/arm,zynpu.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/staging/arm,zynpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM ZHOUYI AI accelerator bindings + +maintainers: + - Cai Huoqing + +description: + Supports ZHOUYI AI accelerator in ARM SOC. + +properties: + compatible: + const: armchina,zhouyi-v1 + + reg: + maxItems: 1 + + device_type: + const: zynpu + + cma-reserved-bytes: + default: 0 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 3 + +required: + - compatible + - reg + - device_type + - cma-reserved-bytes + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + zynpu@03050000 { + compatible = "armchina,zhouyi-v1"; + reg = <0x0 0x03050000 0x0 0x1000>; + device_type = "zynpu"; + cma-reserved-bytes = <0x2600000>; + interrupts = ; + clocks = <&clk_zynpu>, + <&clk_pll_zynpu>, + <&clk_zynpu_slv>; + }; + }; +... -- 2.25.1