Date:   Thu, 25 Nov 2021 10:40:34 +0530
From:   Vinod Koul <vkoul@kernel.org>
To:     Swapnil Kashinath Jakhade <sjakhade@cadence.com>
Cc:     "kishon@ti.com" <kishon@ti.com>,
        "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
        "linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        Milind Parab <mparab@cadence.com>,
        "a-govindraju@ti.com" <a-govindraju@ti.com>
Subject: Re: [PATCH v3 13/15] phy: cadence: Sierra: Add PCIe + QSGMII PHY
 multilink configuration
Message-ID: <YZ8aygJQoxie+Ddn@matsya>
References: <20211022170236.18839-1-sjakhade@cadence.com>
 <20211022170236.18839-14-sjakhade@cadence.com>
 <YZxyja2xEkpWvStR@matsya>
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On 24-11-21, 07:33, Swapnil Kashinath Jakhade wrote:

> > so this is pcie->qsgmii ->ssc/external/internal ... ok
> > 
> > > +				[NO_SSC] =
> > &pcie_100_no_ssc_plllc_cmn_vals,
> > > +				[EXTERNAL_SSC] =
> > &pcie_100_ext_ssc_plllc_cmn_vals,
> > > +				[INTERNAL_SSC] =
> > &pcie_100_int_ssc_plllc_cmn_vals,
> > > +			},
> > >  		},
> > >  		[TYPE_USB] = {
> > >  			[TYPE_NONE] = {
> > >  				[EXTERNAL_SSC] =
> > &usb_100_ext_ssc_cmn_vals,
> > >  			},
> > >  		},
> > > +		[TYPE_QSGMII] = {
> > > +			[TYPE_PCIE] = {
> > 
> > now it is reverse! qsgmii -> pcie -> ... why?
> > 
> > what is meant by pcie->qsgmii and qsgmii-> pcie?
> > 
> 
> Multi-protocol configuration is done in 2 phases, each for one protocol.
> e.g. for PCIe + QSGMII case,
> [TYPE_PCIE][TYPE_QSGMII] will configure common and lane registers for PCIe and
> [TYPE_QSGMII][TYPE_PCIE] will configure common and lane registers for QSGMII.

Then it should be always common + protocol or protocol + common, not
both please! Pls make an order and stick to it everywhere... If that is
not possible, I would like to understand why

-- 
~Vinod