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[131.111.5.141]) by smtp.gmail.com with ESMTPSA id l15sm3313235wme.47.2021.11.25.08.08.03 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Nov 2021 08:08:04 -0800 (PST) Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 14.0 \(3654.120.0.1.13\)) Subject: Re: [PATCH] dt-bindings: interrupt-controller: sifive, plic: Fix number of interrupts From: Jessica Clarke In-Reply-To: <20211125152233.162868-1-geert@linux-m68k.org> Date: Thu, 25 Nov 2021 16:08:03 +0000 Cc: Thomas Gleixner , Marc Zyngier , Rob Herring , Palmer Dabbelt , Paul Walmsley , Sagar Kadam , "linux-kernel@vger.kernel.org List" , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Content-Transfer-Encoding: quoted-printable Message-Id: <161F972E-7972-4001-BE19-C88F81EF8047@jrtc27.com> References: <20211125152233.162868-1-geert@linux-m68k.org> To: Geert Uytterhoeven X-Mailer: Apple Mail (2.3654.120.0.1.13) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 25 Nov 2021, at 15:22, Geert Uytterhoeven = wrote: >=20 > To improve human readability and enable automatic validation, the = tuples > in "interrupts-extended" properties should be grouped using angle > brackets. As the DT bindings lack an upper bound on the number of > interrupts, thus assuming one, proper grouping is currently flagged as > an error. >=20 > Fix this by adding the missing "maxItems", limiting it to 9 interrupts > (one interrupt for a system management core, and two interrupts per = core > for other cores), which should be sufficient for now. This is SiFive=E2=80=99s IP, so is this actually true? I would imagine = it=E2=80=99s just parameterised and could be generated with as many targets as fit in the MMIO space, and that this is thus inaccurate. Besides, such a function change should be made separately from the grouping change. The same goes for your equivalent sifive,clint0 patch. Jess > Group the tuples in the example. >=20 > Signed-off-by: Geert Uytterhoeven > --- > .../interrupt-controller/sifive,plic-1.0.0.yaml | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) >=20 > diff --git = a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0= .yaml = b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0= .yaml > index 08d5a57ce00ff446..198b373f984f3438 100644 > --- = a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0= .yaml > +++ = b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0= .yaml > @@ -61,6 +61,7 @@ properties: >=20 > interrupts-extended: > minItems: 1 > + maxItems: 9 > description: > Specifies which contexts are connected to the PLIC, with "-1" = specifying > that a context is not present. Each node pointed to should be a > @@ -89,12 +90,11 @@ examples: > #interrupt-cells =3D <1>; > compatible =3D "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; > interrupt-controller; > - interrupts-extended =3D < > - &cpu0_intc 11 > - &cpu1_intc 11 &cpu1_intc 9 > - &cpu2_intc 11 &cpu2_intc 9 > - &cpu3_intc 11 &cpu3_intc 9 > - &cpu4_intc 11 &cpu4_intc 9>; > + interrupts-extended =3D <&cpu0_intc 11>, > + <&cpu1_intc 11>, <&cpu1_intc 9>, > + <&cpu2_intc 11>, <&cpu2_intc 9>, > + <&cpu3_intc 11>, <&cpu3_intc 9>, > + <&cpu4_intc 11>, <&cpu4_intc 9>; > reg =3D <0xc000000 0x4000000>; > riscv,ndev =3D <10>; > }; > --=20 > 2.25.1 >=20 >=20 > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv