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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: bp.renesas.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: OSZPR01MB7019.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8e7d06c3-9a80-49e8-0541-08d9b13ed6ba X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Nov 2021 00:42:49.4675 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: hmPxAhGa5BQtUI8dYf4SSsD6wSmU5cC4qZUIJnoVa1vZA7TKdonAKkcr8tsWvvkAN512wdC+F1qKe9tWZrvWgfjKKGEQQa0JOTf+bcJGIEgs3OmG3lORp8bQcx3k8Wjx X-MS-Exchange-Transport-CrossTenantHeadersStamped: OS0PR01MB6338 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Marc, > -----Original Message----- > From: Marc Zyngier > Sent: 23 November 2021 09:11 > To: Geert Uytterhoeven > Cc: linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; kernel-team= @android.com; Rob Herring > ; John Crispin ; Biwen Li ; Chris Brandt > ; linux-renesas-soc@vger.kernel.org; Prabhakar = Mahadev Lad > > Subject: Re: [PATCH] of/irq: Add a quirk for controllers with their own d= efinition of interrupt-map >=20 > On Tue, 23 Nov 2021 08:44:19 +0000, > Geert Uytterhoeven wrote: > > > > Hi Marc, > > > > On Tue, Nov 23, 2021 at 9:33 AM Marc Zyngier wrote: > > > On Tue, 23 Nov 2021 07:57:48 +0000, > > > Geert Uytterhoeven wrote: > > > > Summarized: > > > > - Before the bad commit, and after your fix, irqc-rza1 is invoked= , > > > > and the number of interrupts seen is correct, but input events > > > > are doubled. > > > > - After the bad commit, irqc-rza1 is not invoked, and there is an > > > > interrupt storm, but input events are OK. > > > > > > OK, that's reassuring, even if the "twice the events" stuff isn't > > > what you'd expect. We at least know this is a separate issue, and > > > that this patch on top of -rc1 brings you back to the 5.15 behaviour. > > > > > > I'd expect it to be the case for the other platforms as well. > > > > OK. > > > > BTW, what would have been the correct way to do this for irqc-rza1? > > I think we're about to make the same mistake with RZ/G2L IRQC > > support[1]? >=20 > Indeed, and I was about to look into it. >=20 > There are multiple ways to skin this cat, including renaming 'interrupt-m= ap' to 'my-own-private- > interrupt-map'. Or use something akin the new 'msi-range' (which we could= call interrupt-range), and > replace: >=20 > interrupt-map =3D <0 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, > <1 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, > <2 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, > <3 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, > <4 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, > <5 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, > <6 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, > <7 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; >=20 > with: >=20 > interrupt-range =3D <&gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0 8>; >=20 Just to clarify, do you suggest to add interrupt-range as a generic DT prop= erty or SoC/company specific property? If you meant to add generic property= where would you suggest to document this property? Maybe to chime in with "msi-ranges" we could name it to "interrupt-ranges"? Cheers, Prabhakar > which reads as "base interrupt spec", "start pin", "count". This gives y= ou almost the same level of > information, and doesn't interfere with the rest of the DT properties. Pa= rsing it is also much > simpler. > But that's up to you, really. >=20 > M. >=20 > -- > Without deviation from the norm, progress is not possible.