From:   Leo Li <leoyang.li@nxp.com>
To:     Rob Herring <robh@kernel.org>
CC:     Bjorn Helgaas <bhelgaas@google.com>,
        "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "Z.Q. Hou" <zhiqiang.hou@nxp.com>
Subject: RE: [PATCH 4/4] dt-bindings: pci: layerscape-pci: define aer/pme
 interrupts
Thread-Topic: [PATCH 4/4] dt-bindings: pci: layerscape-pci: define aer/pme
 interrupts
Thread-Index: AQHX3aPddDH3ddPt8EuZqS4SQ5nFIKwbYVKAgAAXieA=
Date:   Tue, 30 Nov 2021 03:35:51 +0000
Message-ID: <AS8PR04MB89467DDB9BC3217431716D358F679@AS8PR04MB8946.eurprd04.prod.outlook.com>
References: <20211120001621.21246-1-leoyang.li@nxp.com>
 <20211120001621.21246-5-leoyang.li@nxp.com>
 <YaWGKaBvTpx1pA/x@robh.at.kernel.org>
In-Reply-To: <YaWGKaBvTpx1pA/x@robh.at.kernel.org>
Accept-Language: en-US
Content-Language: en-US
x-ms-exchange-antispam-messagedata-chunkcount: 1
x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?jzLfUyyayXQDjHqk/EGvbfODVPJisyJ7b8aJbbAMiDQgH80JnU9z4E/ThWPl?=
 =?us-ascii?Q?cngoXVxqC96jzGCyApie8jnxwzW2Wr/6lQvWu5Tzvef5nJK9OXLEa4pCNnyt?=
 =?us-ascii?Q?6RBi3vvdZlSnzi587FUNpSdH49CdcUbHojpmXUKNYPDY4B1mBBUWvlSNvO0f?=
 =?us-ascii?Q?kJOrUA0nQIheWaX7pzQLl7NUp8GCzL1C6iF/9O3Is8W5RIpgXxTluovVxYWv?=
 =?us-ascii?Q?CDmJMQbE+bOVwvsBv+96DNc5EriMJzFdfbLhd/fspa46/7AYkd6WjB1xoriK?=
 =?us-ascii?Q?S9Qdp4UEYns7gNTsDpqWQKr+XUP8xsZN4ZAeInb8l36cP25+4okuF6TBOJkc?=
 =?us-ascii?Q?fZu3uPBO1plBEnUmdmtvVRV+F0fGONkkULGZaBGG+KuoxP5YaDMa6mZVPYU9?=
 =?us-ascii?Q?lq0s9g7ppzfyXxtgMC7b7J65nd/X95z3dJac0tRJ/AOKQmhQSqPyNIn7toN4?=
 =?us-ascii?Q?F7kAknSf5cmMvSONmiSLa57dui6pOGeE7miswl6kybl2z+9zXajcXXx56qSP?=
 =?us-ascii?Q?g5sXJ5YOk2nFTHGhHMujMc3/+q0Qa7WsH+dFbqWNozGAzg3xUK06mEKcYqnI?=
 =?us-ascii?Q?god8PAxVlmk+sIfAQRv6+ajhzY2QlLbqeLugAqkVBfJ+TFM0uUE37BI2W8nk?=
 =?us-ascii?Q?NBE1vv+0YwESE7Pjzrgu2zbDJv+rjV5LHSOvqk+H6nzddaJxUnXwerXge7D1?=
 =?us-ascii?Q?wHAwghV+Z1n+icfjYRIWCd+SGX6uyftOYA7bXww5CnOC6sL0ARzA1FONHAbs?=
 =?us-ascii?Q?y0k2cJ1icBTBRHUmSRw8bz5peOY3QBNe9kE/utfy4BRiaSIJrZGljSGSn9Cb?=
 =?us-ascii?Q?fcNaQluUzre2RQ2rmJ29kQdGUqR9KBx2/Se3Sa//Eij1mHa5raxgNwxPFR7S?=
 =?us-ascii?Q?DxLK0N21XJWFvUZFLYLer9ehBvO+YsihKqAUi1fTSsAnaAXEcUDq/NSyEyvW?=
 =?us-ascii?Q?ph4q2rzfau82n0UkZ0YFiJ47PScLop9KOEV15cdK3aK1DXoZC5hxkMFjAvXQ?=
 =?us-ascii?Q?etwqRAAKREo3Ow5ykj/6w1oYaGXRbTn45Rbv8LP1e9+Pi4ABMnPX/paFXZsX?=
 =?us-ascii?Q?ypVsEEKJn5d3SLwEsBFD2rxKMTMe1BkNxrw7OHatopBuikmSwAEnlTaRCqfJ?=
 =?us-ascii?Q?NnRzGmL7WSNsyc77975HGjKwk6Mm7xmeSNiQmyC0kP6EcuLJdWBqHgEj/2HH?=
 =?us-ascii?Q?5WxvtkMKj2YN8wOJ5zrQBKRbROi/EnVrtKULy2XMi6AwNWj22VboGt5otaUP?=
 =?us-ascii?Q?TD+QcmA40A7MQk/MipLXwN7d/IpS9JOTlkcyl3UlvR8/pNSov2LFIJ5GW2qP?=
 =?us-ascii?Q?pi+c8aKRWydrZRc3FyOZT0gyz4I7qc3TLGBbazFmmmQyrR3y8A7JtUwoB7Mm?=
 =?us-ascii?Q?jWSuTo0m4cGDs2AJEmvP54PqS1DzDkN3xLSLy3joNVpI1hRWScUxOQpieYXq?=
 =?us-ascii?Q?qOb2IRLWVeB6YYhopzLl+BfaaHhlujhcirduTFQV4303pWQcx8wzwewW4K1C?=
 =?us-ascii?Q?RzWwucjgzhVKDdSS05z/W8IcoHj/kE1gvQ1YtLXrayYNeZgrpksflfxSe9bU?=
 =?us-ascii?Q?kFm/nIj7Z8nmj7g1DR79mPyL641jzLkuUfxtUQC/JsqIQDRseNVS/nxA0qO8?=
 =?us-ascii?Q?8w=3D=3D?=
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-OriginatorOrg: nxp.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-AuthSource: AS8PR04MB8946.eurprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 66ae4344-e66c-4ade-2de5-08d9b3b28209
X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Nov 2021 03:35:51.6178
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-CrossTenant-userprincipalname: jQbCn8KdqMw9QNKaPEnqw+s+oUF/zdHgO6UXB3xVBOrxAPzhYrCs9ycVgsL+11jOlr+ehuMbouSo5HBrvFoVgA==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR04MB8466
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org


> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Monday, November 29, 2021 8:02 PM
> To: Leo Li <leoyang.li@nxp.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>; linux-pci@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Z.Q. Hou
> <zhiqiang.hou@nxp.com>
> Subject: Re: [PATCH 4/4] dt-bindings: pci: layerscape-pci: define aer/pme
> interrupts
>=20
> On Fri, Nov 19, 2021 at 06:16:21PM -0600, Li Yang wrote:
> > Some platforms using this controller have separated interrupt lines
> > for aer or pme events instead of having a single interrupt line for
> > miscellaneous events.  Define interrupts in the binding for these
> > interrupt lines.
> >
> > Signed-off-by: Li Yang <leoyang.li@nxp.com>
> > ---
> >  .../devicetree/bindings/pci/layerscape-pci.txt     | 14 ++++++++++----
> >  1 file changed, 10 insertions(+), 4 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > index 8fd6039a826b..bcf11bfc4bab 100644
> > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > @@ -31,8 +31,13 @@ Required properties:
> >  - reg: base addresses and lengths of the PCIe controller register bloc=
ks.
> >  - interrupts: A list of interrupt outputs of the controller. Must cont=
ain an
> >    entry for each entry in the interrupt-names property.
> > -- interrupt-names: Must include the following entries:
> > -  "intr": The interrupt that is asserted for controller interrupts
> > +- interrupt-names: It could include the following entries:
> > +  "aer": For interrupt line reporting aer events when non MSI/MSI-X/IN=
Tx
> mode
> > +		is used
> > +  "pme": For interrupt line reporting pme events when non MSI/MSI-
> X/INTx mode
> > +		is used
> > +  "intr": For interrupt line reporting miscellaneous controller
> > +events
> > +  ......
> >  - fsl,pcie-scfg: Must include two entries.
> >    The first entry must be a link to the SCFG device node
> >    The second entry is the physical PCIe controller index starting from=
 '0'.
> > @@ -52,8 +57,9 @@ Example:
> >  		reg =3D <0x00 0x03400000 0x0 0x00010000   /* controller
> registers */
> >  		       0x40 0x00000000 0x0 0x00002000>; /* configuration space
> */
> >  		reg-names =3D "regs", "config";
> > -		interrupts =3D <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /*
> controller interrupt */
> > -		interrupt-names =3D "intr";
> > +		interrupts =3D <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, /* aer
> interrupt */
> > +			<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* pme
> interrupt */
> > +		interrupt-names =3D "aer", "pme";
>=20
> This isn't a compatible change. The h/w suddenly has no 'intr'
> interrupt?

The original 'intr' was just a place holder for a HW interrupt signal witho=
ut a clear definition of events associated.  Some later SoC has more interr=
upt signals to associate with more specific events.

If needed, we can keep the "intr" interrupt-name there just for backward co=
mpatibility although it was never used in Linux.

>=20
> >  		fsl,pcie-scfg =3D <&scfg 0>;
> >  		#address-cells =3D <3>;
> >  		#size-cells =3D <2>;
> > --
> > 2.25.1
> >
> >