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Mon, 29 Nov 2021 21:56:10 -0800 From: Srinivas Neeli To: , , , , , CC: , , , , Srinivas Neeli Subject: [PATCH V3 2/2] rtc: zynqmp: Add calibration set and get support Date: Tue, 30 Nov 2021 11:25:41 +0530 Message-ID: <20211130055541.2789-2-srinivas.neeli@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211130055541.2789-1-srinivas.neeli@xilinx.com> References: <20211130055541.2789-1-srinivas.neeli@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1355d9e7-6186-40e1-e231-08d9b3c62122 X-MS-TrafficTypeDiagnostic: SJ0PR02MB8675: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:6790; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 08os37MHqIketBrr8vZeOt7D06SbtfmkaPIKoInLiPQODJ1ES6BGiySgvKSvcSJ96UYLcWwOIuqy6FMTP0UjvD2U/ABuMIDsOb6I6MnV7Kve2g9Ml9ugjzUyYg2LPqmzqkzf43WMC08G3AA2Ndfc3fKtwIy+JlFb0M3nG+bNln9NCNc50/1RF5yKEDGkeuvpLmUtagllzlPXAToRN411YaJ/HIiME9r1qSLKVXTzJvHiqufIV3aEXWxBmRqScEPulWVL1H/3Uwcua50uiA/7uAUgl/5QJaPYJ+ZCAWiOv5RpsYUx1lRSYdpI9vnm28vVheVNF19/X5K7rPC/Wqa6OuwFx20pEAMX3lESlkNKnwDj+ec3enGE0ex8geV/vvDc8aZmj06qQsQva6dKcNV+5hirR0umxhHAcVcLBQck8yr9V8TAtmZY24Spk6Np/a/s+AsiggjqYaiJsrdH+FWVzv4uCc/PjvJqAdxnB5yX6wZ8GldNUd6ih5smgL5gaHzbO3Be72Q98PXT0Gl54R9ndSxkjbKNfYNUGL16lT746nmnRKALQAt/gdfjzrmaJKbY30PliLc5W81/eUkrOTvL2KzFOlTruCG3+Y3fMpllpWwygUpSoR4UhG5244m7IiLoh5mvz9fLN1VsyCuuwkMySaueZ+UqK/kscJbw2a1FOeq/lXPhrZiUPHJ5eiU5ww5qnKfBe9xaXmr6j35YBuAM8Z80CpWWs0RNQCXRNEBRBLFBB7QDyg193fCl1c4QAUqH X-Forefront-Antispam-Report: CIP:149.199.62.198;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapexch01.xlnx.xilinx.com;PTR:unknown-62-198.xilinx.com;CAT:NONE;SFS:(46966006)(36840700001)(47076005)(7636003)(426003)(83380400001)(107886003)(36756003)(8936002)(7696005)(44832011)(8676002)(356005)(9786002)(70586007)(5660300002)(4326008)(26005)(2906002)(508600001)(6636002)(316002)(186003)(82310400004)(1076003)(6666004)(110136005)(336012)(36860700001)(2616005)(54906003)(70206006)(102446001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 05:56:18.9666 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1355d9e7-6186-40e1-e231-08d9b3c62122 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0062.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR02MB8675 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Zynqmp RTC controller has a calibration feature to compensate time deviation due to input clock inaccuracy. Set and get calibration API's are used for setting and getting calibration value from the controller calibration register. Signed-off-by: Srinivas Neeli --- Changes in V3: -Calculated tick_mult using crystal frequency. -Calibration register updating based on crystal frequency in probe. -Supressed MIN an MAX calibration values,Will send separate patch in future. Changes in V2: -Removed unused macro. -Updated code with review comments. --- drivers/rtc/rtc-zynqmp.c | 104 +++++++++++++++++++++++++++++++-------- 1 file changed, 84 insertions(+), 20 deletions(-) diff --git a/drivers/rtc/rtc-zynqmp.c b/drivers/rtc/rtc-zynqmp.c index f440bb52be92..eb6ee55ca725 100644 --- a/drivers/rtc/rtc-zynqmp.c +++ b/drivers/rtc/rtc-zynqmp.c @@ -6,6 +6,7 @@ * */ +#include #include #include #include @@ -36,17 +37,21 @@ #define RTC_OSC_EN BIT(24) #define RTC_BATT_EN BIT(31) -#define RTC_CALIB_DEF 0x198233 +#define RTC_CALIB_DEF 0x8000 #define RTC_CALIB_MASK 0x1FFFFF #define RTC_ALRM_MASK BIT(1) #define RTC_MSEC 1000 +#define RTC_FR_MASK 0xF0000 +#define RTC_FR_MAX_TICKS 16 +#define RTC_PPB 1000000000LL struct xlnx_rtc_dev { struct rtc_device *rtc; void __iomem *reg_base; int alarm_irq; int sec_irq; - unsigned int calibval; + struct clk *rtc_clk; + unsigned int freq; }; static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm) @@ -61,13 +66,6 @@ static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm) */ new_time = rtc_tm_to_time64(tm) + 1; - /* - * Writing into calibration register will clear the Tick Counter and - * force the next second to be signaled exactly in 1 second period - */ - xrtcdev->calibval &= RTC_CALIB_MASK; - writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR)); - writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR); /* @@ -173,15 +171,71 @@ static void xlnx_init_rtc(struct xlnx_rtc_dev *xrtcdev) rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL); rtc_ctrl |= RTC_BATT_EN; writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL); +} - /* - * Based on crystal freq of 33.330 KHz - * set the seconds counter and enable, set fractions counter - * to default value suggested as per design spec - * to correct RTC delay in frequency over period of time. +static int xlnx_rtc_read_offset(struct device *dev, long *offset) +{ + struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev); + long offset_val = 0; + unsigned int tick_mult = RTC_PPB / xrtcdev->freq; + unsigned int calibval; + + calibval = readl(xrtcdev->reg_base + RTC_CALIB_RD); + /* Offset with seconds ticks */ + offset_val = calibval & RTC_TICK_MASK; + offset_val = offset_val - RTC_CALIB_DEF; + offset_val = offset_val * tick_mult; + + /* Offset with fractional ticks */ + if (calibval & RTC_FR_EN) + offset_val += ((calibval & RTC_FR_MASK) >> RTC_FR_DATSHIFT) + * (tick_mult / RTC_FR_MAX_TICKS); + *offset = offset_val; + + return 0; +} + +static int xlnx_rtc_set_offset(struct device *dev, long offset) +{ + struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev); + short int max_tick; + unsigned char fract_tick = 0; + unsigned int calibval; + int fract_offset; + unsigned int tick_mult = RTC_PPB / xrtcdev->freq; + + /* Number ticks for given offset */ + max_tick = div_s64_rem(offset, tick_mult, &fract_offset); + + /* Number fractional ticks for given offset */ + if (fract_offset) { + if (fract_offset < 0) { + fract_offset = fract_offset + tick_mult; + max_tick--; + } + if (fract_offset > (tick_mult / RTC_FR_MAX_TICKS)) { + for (fract_tick = 1; fract_tick < 16; fract_tick++) { + if (fract_offset <= + (fract_tick * + (tick_mult / RTC_FR_MAX_TICKS))) + break; + } + } + } + + /* Zynqmp RTC uses second and fractional tick + * counters for compensation */ - xrtcdev->calibval &= RTC_CALIB_MASK; - writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR)); + calibval = max_tick + RTC_CALIB_DEF; + + if (fract_tick) + calibval |= RTC_FR_EN; + + calibval |= (fract_tick << RTC_FR_DATSHIFT); + + writel(calibval, (xrtcdev->reg_base + RTC_CALIB_WR)); + + return 0; } static const struct rtc_class_ops xlnx_rtc_ops = { @@ -190,6 +244,8 @@ static const struct rtc_class_ops xlnx_rtc_ops = { .read_alarm = xlnx_rtc_read_alarm, .set_alarm = xlnx_rtc_set_alarm, .alarm_irq_enable = xlnx_rtc_alarm_irq_enable, + .read_offset = xlnx_rtc_read_offset, + .set_offset = xlnx_rtc_set_offset, }; static irqreturn_t xlnx_rtc_interrupt(int irq, void *id) @@ -255,10 +311,18 @@ static int xlnx_rtc_probe(struct platform_device *pdev) return ret; } - ret = of_property_read_u32(pdev->dev.of_node, "calibration", - &xrtcdev->calibval); - if (ret) - xrtcdev->calibval = RTC_CALIB_DEF; + /* Getting the rtc_clk info */ + xrtcdev->rtc_clk = devm_clk_get_optional(&pdev->dev, "rtc_clk"); + if (IS_ERR(xrtcdev->rtc_clk)) { + if (PTR_ERR(xrtcdev->rtc_clk) != -EPROBE_DEFER) + dev_warn(&pdev->dev, "Device clock not found.\n"); + } + xrtcdev->freq = clk_get_rate(xrtcdev->rtc_clk); + if (!xrtcdev->freq) + xrtcdev->freq = RTC_CALIB_DEF; + ret = readl(xrtcdev->reg_base + RTC_CALIB_RD); + if (!ret) + writel(xrtcdev->freq, (xrtcdev->reg_base + RTC_CALIB_WR)); xlnx_init_rtc(xrtcdev); -- 2.17.1