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Tue, 30 Nov 2021 08:01:22 +0000 Message-ID: Date: Tue, 30 Nov 2021 13:31:17 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.3.2 Subject: Re: [PATCH v2 2/6] arm64: dts: xilinx: zynqmp: Add RPU subsystem device node Content-Language: en-US To: Mathieu Poirier CC: Bjorn Andersson , Rob Herring , Michal Simek , "Laurent Pinchart" , Ben Levinsky , Bill Mills , "Sergei Korneichuk" , , , , References: <20211123062050.1442712-1-tanmay.shah@xilinx.com> <20211123062050.1442712-3-tanmay.shah@xilinx.com> <20211129175803.GB676889@p14s> From: Tanmay Shah In-Reply-To: <20211129175803.GB676889@p14s> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7990087a-ff20-4e77-3332-08d9b3d79aee X-MS-TrafficTypeDiagnostic: MWHPR02MB2688: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:8273; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 08:01:24.6079 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7990087a-ff20-4e77-3332-08d9b3d79aee X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.80.198];Helo=[xir-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT021.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR02MB2688 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Mathieu, Thanks for reviews. Please find my responses inline. On 11/29/21 11:28 PM, Mathieu Poirier wrote: > On Mon, Nov 22, 2021 at 10:20:46PM -0800, Tanmay Shah wrote: >> RPU subsystem can be configured in cluster-mode or split mode. >> Also each r5 core has separate power domains. >> >> Signed-off-by: Tanmay Shah >> --- >> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 17 +++++++++++++++++ >> 1 file changed, 17 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >> index 28dccb891a53..f4fb98ccb1b5 100644 >> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >> @@ -654,6 +654,23 @@ qspi: spi@ff0f0000 { >> power-domains = <&zynqmp_firmware PD_QSPI>; >> }; >> >> + r5fss: r5fss@ff9a0000 { >> + compatible = "xlnx,zynqmp-r5fss"; >> + xlnx,cluster-mode = <1>; >> + >> + reg = <0x0 0Xff9a0000 0x0 0x228>; > This line is giving me an obvious checkpatch warning. Please make sure you run > checkpatch.pl before sending out a patchset. > I ran checkpatch.pl on patches that contains .c files and .h files and I had fixed lot of style related warnings using checkpatch.pl. However, I had misunderstanding that checkpatch.pl should not be used for patches with .yaml and .dtsi files. So I skipped it for bindings patch and dtsi patch. Thanks for correcting me here. I will make sure to run checkpatch.pl for all patches from here. Also, I will fix this error in next revision. >> + >> + r5f_core0: r5f-0 { >> + compatible = "xlnx,zynqmp-r5f"; >> + power-domains = <&zynqmp_firmware PD_RPU_0>; >> + }; >> + >> + r5f_core1: r5f-1 { >> + compatible = "xlnx,zynqmp-r5f"; >> + power-domains = <&zynqmp_firmware PD_RPU_1>; >> + }; >> + }; >> + >> psgtr: phy@fd400000 { >> compatible = "xlnx,zynqmp-psgtr-v1.1"; >> status = "disabled"; >> -- >> 2.25.1 >>