Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A0B8C433F5 for ; Tue, 30 Nov 2021 19:59:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343562AbhK3UC1 (ORCPT ); Tue, 30 Nov 2021 15:02:27 -0500 Received: from relay04.th.seeweb.it ([5.144.164.165]:37989 "EHLO relay04.th.seeweb.it" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239950AbhK3UC1 (ORCPT ); Tue, 30 Nov 2021 15:02:27 -0500 Received: from [10.1.250.9] (riviera.nat.ds.pw.edu.pl [194.29.137.1]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id 91811201DF; Tue, 30 Nov 2021 20:59:04 +0100 (CET) Message-ID: Date: Tue, 30 Nov 2021 20:59:03 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.3.2 Subject: Re: [PATCH 04/16] arm64: dts: qcom: sm8350: Specify clock-frequency for arch timer To: Stephen Boyd , ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20211114012755.112226-1-konrad.dybcio@somainline.org> <20211114012755.112226-4-konrad.dybcio@somainline.org> <20211130020536.52D0FC53FC7@smtp.kernel.org> From: Konrad Dybcio In-Reply-To: <20211130020536.52D0FC53FC7@smtp.kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 30/11/2021 03:05, Stephen Boyd wrote: > Quoting Konrad Dybcio (2021-11-13 17:27:43) >> Arch timer runs at 19.2 MHz. Specify the rate in the timer node. >> >> Signed-off-by: Konrad Dybcio >> --- >> arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi >> index a30ba3193d84..60866a20a55c 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi >> @@ -2484,5 +2484,6 @@ timer { >> , >> , >> ; >> + clock-frequency = <19200000>; > Does the firmware not set the frequency properly? It does on my device on the current firmware version (it wouldn't really boot if it didn't, no?), but who knows if it always will, or if it always has been.. It's present in downstream too, so I reckon it does not hurt to have it here too, even for completeness-of-describing-the-machine-properly sake. Konrad