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[66.90.148.213]) by smtp.gmail.com with ESMTPSA id r22sm3901040oij.36.2021.11.30.14.32.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Nov 2021 14:32:24 -0800 (PST) Received: (nullmailer pid 3130635 invoked by uid 1000); Tue, 30 Nov 2021 22:32:23 -0000 Date: Tue, 30 Nov 2021 16:32:23 -0600 From: Rob Herring To: Dipen Patel Cc: thierry.reding@gmail.com, jonathanh@nvidia.com, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-gpio@vger.kernel.org, linus.walleij@linaro.org, bgolaszewski@baylibre.com, warthog618@gmail.com, devicetree@vger.kernel.org, linux-doc@vger.kernel.org Subject: Re: [RFC v3 07/12] dt-bindings: gpio: Add hardware-timestamp-engine property Message-ID: References: <20211123193039.25154-1-dipenp@nvidia.com> <20211123193039.25154-8-dipenp@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211123193039.25154-8-dipenp@nvidia.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Nov 23, 2021 at 11:30:34AM -0800, Dipen Patel wrote: > Some GPIO controllers can timestamp GPIO lines in real time using > hardware timestamp engine. The optional property is added to facilitate > this feature. > > The nvidia GPIO controller has hardware timestamp engine as a backend > to timestamp its GPIO lines in a real time. This change set adds > hardware-timestamp-engine property to reflect that fact. > > Signed-off-by: Dipen Patel > --- > Documentation/devicetree/bindings/gpio/gpio.txt | 8 ++++++++ > .../devicetree/bindings/gpio/nvidia,tegra186-gpio.txt | 7 +++++++ > 2 files changed, 15 insertions(+) > > diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt > index a8895d339bfe..c6ae2eaf5762 100644 > --- a/Documentation/devicetree/bindings/gpio/gpio.txt > +++ b/Documentation/devicetree/bindings/gpio/gpio.txt > @@ -167,6 +167,13 @@ left to right from the passed array. An incomplete array (where the number > of passed named are less than ngpios) will still be used up until the last > provided valid line index. > > +Optionally, a GPIO controller may have a "hardware-timestamp-engine" property. > +This specifies the timestamp engine node. The property is only useful if the > +hardware timestamp engine (HTE) serves as a back-end to support hardware > +timestamp GPIO lines in a real time and GPIO controller has dependency on the > +engine. It will be up to GPIO controller and HTE provider drivers to figure out > +the mapping between GPIO controller and HTE namespaces of a given GPIO line. This needs to be added to schema instead (in dtschema). I find the 'hardware-' part to be redundant. What other type of timestamp engine are we going to have in the h/w description? > + > Example: > > gpio-controller@00000000 { > @@ -180,6 +187,7 @@ gpio-controller@00000000 { > "LED G", "LED B", "Col A", "Col B", "Col C", "Col D", > "Row A", "Row B", "Row C", "Row D", "NMI button", > "poweroff", "reset"; > + hardware-timestamp-engine = <&hadrware_ts_engine_node>; > } > > The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism > diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.txt b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.txt > index adff16c71d21..20f6c9e69839 100644 > --- a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.txt > +++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.txt > @@ -127,6 +127,12 @@ Required properties: > - 8: Active low level-sensitive. > Valid combinations are 1, 2, 3, 4, 8. > > +Optional properties: > +- hardware-timestamp-engine > + AON GPIO controller has timestamp engine which can hardware timestamp > + GPIO configured as input and IRQ. This property specifies hardware > + timestamp engine (HTE) device-tree node. > + > Example: > > #include > @@ -162,4 +168,5 @@ gpio@c2f0000 { > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > + hardware-timestamp-engine = <&tegra_hte_aon>; > }; > -- > 2.17.1 > >