Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBB03C433EF for ; Wed, 1 Dec 2021 03:09:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346426AbhLADNF (ORCPT ); Tue, 30 Nov 2021 22:13:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346415AbhLADNE (ORCPT ); Tue, 30 Nov 2021 22:13:04 -0500 X-Greylist: delayed 164 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Tue, 30 Nov 2021 19:09:43 PST Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E040AC061574 for ; Tue, 30 Nov 2021 19:09:43 -0800 (PST) Received: by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 62C92300089; Wed, 1 Dec 2021 03:06:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1638328016; bh=jCn23iMIrHBoRtWjcFw98/gYkwF92XfZiHhfmSCjOoI=; h=Message-ID:Date:Mime-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type:Content-Transfer-Encoding; b=Q4C3aVpjzLvUhcQZ0lsBqlScwT4xWJD5JPZfXmOEtqw95aLEXZhLT54jSOSxqajxK XrcUmoHUNPqB8zy+nMvPcaPpUbV1zU9lCab2Xwqvvj5pIiBKXoUl7yzBSm4wIP/URQ 8w8+niE3DSM0hJaa+cbWdVOL6oSBjwgd4YY/fREE= Message-ID: <1d035613-390c-32c2-aa92-cc0f7797488d@irq.a4lg.com> Date: Wed, 1 Dec 2021 12:06:53 +0900 Mime-Version: 1.0 Subject: Re: [PATCH V4 1/2] dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt Content-Language: en-US To: Atish Patra , Jessica Clarke Cc: Philipp Tomsich , =?UTF-8?Q?Heiko_St=c3=bcbner?= , linux-riscv , Wei Fu , "linux-kernel@vger.kernel.org List" , taiten.peng@canonical.com, Aniket Ponkshe , Gordan Markus , Guo Ren , Arnd Bergmann , Chen-Yu Tsai , Maxime Ripard , Dan Lustig , Greg Favor , Andrea Mondelli , Jonathan Behrens , Xinhaoqu , Bill Huffman , Nick Kossifidis , Allen Baum , Josh Scheid , Richard Trauben , Anup Patel , Rob Herring , Anup Patel , atishp04@gmail.com, Palmer Dabbelt , Guo Ren , =?UTF-8?Q?Christoph_M=c3=bcllner?= , Christoph Hellwig , liush , Wei Wu , Drew Fustini , Heinrich Schuchardt References: <20211129014007.286478-1-wefu@redhat.com> <1909580.k68io2XIxi@diego> <2728314.U2HhIfhhqV@diego> <03B8F784-4AF3-425D-99B6-F753F7970273@jrtc27.com> From: Tsukasa OI In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2021/12/01 10:21, Atish Patra wrote: > On Tue, Nov 30, 2021 at 8:13 AM Jessica Clarke wrote: >> >> On 30 Nov 2021, at 15:01, Philipp Tomsich wrote: >>> >>> We did touch on this in our coordination call a few weeks ago: the >>> grouping under mmu and the bool-entries were chosen because of their >>> similarity to other extensions (i.e. for Zb[abcs] there could/should >>> be a bool-entry under each cpu-node — for some Zv* entries a subnode >>> might be needed with further parameters). >>> >>> The string-based approach (as in the originally proposed "mmu-type=") >>> would like not scale with the proliferation of small & modular >>> extensions. >> >> I don’t see why the Sv* extensions need to be under an mmu node then, >> unless the intent is that every extension be grouped under a sub-node >> (which doesn’t seem viable due to extensions like Zbk*, unless you >> group by Ss, Sv and Z)? >> > > It shouldn't be. All the ISA extensions (i.e. standard, supervisor & hypervisor) > with prefix S,Z,H should be kept separate in a separate node for easy > parsing. "Easy parsing" is not quite convincing. There's a reason other than that I made RFC PATCH to parse multi-letter extensions: v1: v2: (note: those patches will break RISC-V KVM because of possible ISA Manual inconsistency and discussion/resolution needed) (...continued below...) > > "riscv,isa" dt property will not scale at all. Just look at the few > extensions that were ratified this year > and Linux kernel needs to support them. > > "Sscofpmf", "Svpbmt", "Zicbom" > >> Also, what is going to happen to the current riscv,isa? Will that >> continue to exist and duplicate the info, or will kernels be required >> to reconstruct the string themselves if they want to display it to >> users? >> > > This is my personal preference: > riscv,isa will continue to base Standard ISA extensions that have > single letter extensions. > > This new DT node will encode all the non-single letter extensions. > I am not sure if it should include some provisions for custom > extensions starting with X because > that will be platform specific. > > Again, this is just my personal preference. I will try to send a patch > soon so that we can initiate a broader > discussion of the scheme and agree/disagree on something. For supervisor-only extensions like "Svpbmt", new DT node would be a reasonable solution (and I would not directly object about that node). However, there's many multi-letter extensions that are useful for user mode. Because "riscv,isa" is exposed via sysfs and procfs (/proc/cpuinfo), it can be really helpful to have multi-letter extensions. Also, current version of Spike, a RISC-V ISA Simulator puts all multi-letter extensions in "riscv,isa" and I thought this is intended. My preference: (1) Allow having multi-letter extensions and versions in "riscv,isa" (2) Adding new DT node for supervisor-related extensions would be reasonable (but I don't strongly agree/disagree). Thanks, Tsukasa > > > >> As a FreeBSD developer I’m obviously not a part of many of these >> discussions, but what the Linux community imposes as the device tree >> bindings has a real impact on us. >> >> Jess >> >>> On Tue, 30 Nov 2021 at 14:59, Jessica Clarke wrote: >>>> >>>> On 30 Nov 2021, at 13:27, Heiko Stübner wrote: >>>>> >>>>> Hi, >>>>> >>>>> Am Dienstag, 30. November 2021, 14:17:41 CET schrieb Jessica Clarke: >>>>>> On 30 Nov 2021, at 12:07, Heiko Stübner wrote: >>>>>>> >>>>>>> Am Montag, 29. November 2021, 13:06:23 CET schrieb Heiko Stübner: >>>>>>>> Am Montag, 29. November 2021, 09:54:39 CET schrieb Heinrich Schuchardt: >>>>>>>>> On 11/29/21 02:40, wefu@redhat.com wrote: >>>>>>>>>> From: Wei Fu >>>>>>>>>> >>>>>>>>>> Previous patch has added svpbmt in arch/riscv and add "riscv,svpmbt" >>>>>>>>>> in the DT mmu node. Update dt-bindings related property here. >>>>>>>>>> >>>>>>>>>> Signed-off-by: Wei Fu >>>>>>>>>> Co-developed-by: Guo Ren >>>>>>>>>> Signed-off-by: Guo Ren >>>>>>>>>> Cc: Anup Patel >>>>>>>>>> Cc: Palmer Dabbelt >>>>>>>>>> Cc: Rob Herring >>>>>>>>>> --- >>>>>>>>>> Documentation/devicetree/bindings/riscv/cpus.yaml | 10 ++++++++++ >>>>>>>>>> 1 file changed, 10 insertions(+) >>>>>>>>>> >>>>>>>>>> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml >>>>>>>>>> index aa5fb64d57eb..9ff9cbdd8a85 100644 >>>>>>>>>> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml >>>>>>>>>> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml >>>>>>>>>> @@ -63,6 +63,16 @@ properties: >>>>>>>>>> - riscv,sv48 >>>>>>>>>> - riscv,none >>>>>>>>>> >>>>>>>>>> + mmu: >>>>>>>>> >>>>>>>>> Shouldn't we keep the items be in alphabetic order, i.e. mmu before >>>>>>>>> mmu-type? >>>>>>>>> >>>>>>>>>> + description: >>>>>>>>>> + Describes the CPU's MMU Standard Extensions support. >>>>>>>>>> + These values originate from the RISC-V Privileged >>>>>>>>>> + Specification document, available from >>>>>>>>>> + https://riscv.org/specifications/ >>>>>>>>>> + $ref: '/schemas/types.yaml#/definitions/string' >>>>>>>>>> + enum: >>>>>>>>>> + - riscv,svpmbt >>>>>>>>> >>>>>>>>> The privileged specification has multiple MMU related extensions: >>>>>>>>> Svnapot, Svpbmt, Svinval. Shall they all be modeled in this enum? >>>>>>>> >>>>>>>> I remember in some earlier version some way back there was the >>>>>>>> suggestion of using a sub-node instead and then adding boolean >>>>>>>> properties for the supported extensions. >>>>>>>> >>>>>>>> Aka something like >>>>>>>> mmu { >>>>>>>> riscv,svpbmt; >>>>>>>> }; >>>>>>> >>>>>>> For the record, I'm talking about the mail from september >>>>>>> https://lore.kernel.org/linux-riscv/CAAeLtUChjjzG+P8yg45GLZMJy5UR2K5RRBoLFVZhtOaZ5pPtEA@mail.gmail.com/ >>>>>>> >>>>>>> So having a sub-node would make adding future extensions >>>>>>> way nicer. >>>>>> >>>>>> Svpbmt is just an ISA extension, and should be treated like any other. >>>>>> Let’s not invent two different ways of representing that in the device >>>>>> tree. >>>>> >>>>> Heinrich asked how the other extensions should be handled >>>>> (Svnapot, Svpbmt, Svinval), so what do you suggest to do with these? >>>> >>>> Whatever is done for Zb[abcs], Zk*, Zv*, Zicbo*, etc. There may not be >>>> a concrete plan for that yet, but that means you should speak with the >>>> people involved with such extensions and come up with something >>>> appropriate together. >>>> >>>> Jess >>>> >> >> >> _______________________________________________ >> linux-riscv mailing list >> linux-riscv@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-riscv > > > > -- > Regards, > Atish > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv >