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[89.77.68.124]) by smtp.gmail.com with ESMTPSA id c1sm234837ljr.111.2021.12.02.00.28.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 Dec 2021 00:28:19 -0800 (PST) Message-ID: <38601fab-816c-37aa-1839-96fa7c6a3959@canonical.com> Date: Thu, 2 Dec 2021 09:28:18 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.3.1 Subject: Re: [PATCH 5/6] i2c: exynos5: Add bus clock support Content-Language: en-US To: Sam Protsenko , Rob Herring Cc: Jaewon Kim , Chanho Park , David Virag , Youngmin Nam , Wolfram Sang , Arnd Bergmann , linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org References: <20211201190455.31646-1-semen.protsenko@linaro.org> <20211201190455.31646-6-semen.protsenko@linaro.org> From: Krzysztof Kozlowski In-Reply-To: <20211201190455.31646-6-semen.protsenko@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 01/12/2021 20:04, Sam Protsenko wrote: > In new Exynos SoCs (like Exynos850) where HSI2C is implemented as a > part of USIv2 block, there are two clocks provided to HSI2C controller: > - PCLK: bus clock (APB), provides access to register interface > - IPCLK: operating IP-core clock; SCL is derived from this one > > Both clocks have to be asserted for HSI2C to be functional in that case. > > Add code to obtain and enable/disable PCLK in addition to already > handled operating clock. Make it optional though, as older Exynos SoC > variants only have one HSI2C clock. > > Signed-off-by: Sam Protsenko > --- > drivers/i2c/busses/i2c-exynos5.c | 46 ++++++++++++++++++++++++++------ > 1 file changed, 38 insertions(+), 8 deletions(-) > You could use clk_bulk API, but for two clocks, where one is optional, it won't reduce much of code, so I am fine here: Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof