From:   "Chanho Park" <chanho61.park@samsung.com>
To:     "'Sam Protsenko'" <semen.protsenko@linaro.org>,
        "'Krzysztof Kozlowski'" <krzysztof.kozlowski@canonical.com>,
        "'Rob Herring'" <robh+dt@kernel.org>
Cc:     "'Jaewon Kim'" <jaewon02.kim@samsung.com>,
        "'David Virag'" <virag.david003@gmail.com>,
        "'Youngmin Nam'" <youngmin.nam@samsung.com>,
        "'Wolfram Sang'" <wsa@kernel.org>,
        "'Arnd Bergmann'" <arnd@arndb.de>, <linux-i2c@vger.kernel.org>,
        <devicetree@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>, <linux-samsung-soc@vger.kernel.org>
In-Reply-To: <20211201190455.31646-6-semen.protsenko@linaro.org>
Subject: RE: [PATCH 5/6] i2c: exynos5: Add bus clock support
Date:   Thu, 2 Dec 2021 19:30:11 +0900
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References: <20211201190455.31646-1-semen.protsenko@linaro.org>
        <CGME20211201190525epcas2p3f2915664524b53bf72c69f46e1c13844@epcas2p3.samsung.com>
        <20211201190455.31646-6-semen.protsenko@linaro.org>
Precedence: bulk

> In new Exynos SoCs (like Exynos850) where HSI2C is implemented as a part
> of USIv2 block, there are two clocks provided to HSI2C controller:
>   - PCLK: bus clock (APB), provides access to register interface
>   - IPCLK: operating IP-core clock; SCL is derived from this one
> 
> Both clocks have to be asserted for HSI2C to be functional in that case.
> 
> Add code to obtain and enable/disable PCLK in addition to already handled
> operating clock. Make it optional though, as older Exynos SoC variants
> only have one HSI2C clock.
> 
> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>

Reviewed-by: Chanho Park <chanho61.park@samsung.com>

Best Regards,
Chanho Park