From:   Swapnil Kashinath Jakhade <sjakhade@cadence.com>
To:     Vinod Koul <vkoul@kernel.org>
CC:     "kishon@ti.com" <kishon@ti.com>,
        "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
        "linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        Milind Parab <mparab@cadence.com>,
        "a-govindraju@ti.com" <a-govindraju@ti.com>
Subject: RE: [PATCH v3 13/15] phy: cadence: Sierra: Add PCIe + QSGMII PHY
 multilink configuration
Thread-Topic: [PATCH v3 13/15] phy: cadence: Sierra: Add PCIe + QSGMII PHY
 multilink configuration
Thread-Index: AQHXx2bHmQutwPZ9l0Sv3BSHrxD/16wQu9eAgAG6aaCAAXB/AIALkHAQ
Date:   Thu, 2 Dec 2021 14:12:51 +0000
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Hi Vinod,

> -----Original Message-----
> From: Vinod Koul <vkoul@kernel.org>
> Sent: Thursday, November 25, 2021 10:41 AM
> To: Swapnil Kashinath Jakhade <sjakhade@cadence.com>
> Cc: kishon@ti.com; robh+dt@kernel.org; p.zabel@pengutronix.de; linux-
> phy@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; Milind Parab <mparab@cadence.com>; a-
> govindraju@ti.com
> Subject: Re: [PATCH v3 13/15] phy: cadence: Sierra: Add PCIe + QSGMII PHY
> multilink configuration
>=20
> EXTERNAL MAIL
>=20
>=20
> On 24-11-21, 07:33, Swapnil Kashinath Jakhade wrote:
>=20
> > > so this is pcie->qsgmii ->ssc/external/internal ... ok
> > >
> > > > +				[NO_SSC] =3D
> > > &pcie_100_no_ssc_plllc_cmn_vals,
> > > > +				[EXTERNAL_SSC] =3D
> > > &pcie_100_ext_ssc_plllc_cmn_vals,
> > > > +				[INTERNAL_SSC] =3D
> > > &pcie_100_int_ssc_plllc_cmn_vals,
> > > > +			},
> > > >  		},
> > > >  		[TYPE_USB] =3D {
> > > >  			[TYPE_NONE] =3D {
> > > >  				[EXTERNAL_SSC] =3D
> > > &usb_100_ext_ssc_cmn_vals,
> > > >  			},
> > > >  		},
> > > > +		[TYPE_QSGMII] =3D {
> > > > +			[TYPE_PCIE] =3D {
> > >
> > > now it is reverse! qsgmii -> pcie -> ... why?
> > >
> > > what is meant by pcie->qsgmii and qsgmii-> pcie?
> > >
> >
> > Multi-protocol configuration is done in 2 phases, each for one protocol=
.
> > e.g. for PCIe + QSGMII case,
> > [TYPE_PCIE][TYPE_QSGMII] will configure common and lane registers for
> > PCIe and [TYPE_QSGMII][TYPE_PCIE] will configure common and lane
> registers for QSGMII.
>=20
> Then it should be always common + protocol or protocol + common, not
> both please! Pls make an order and stick to it everywhere... If that is n=
ot
> possible, I would like to understand why
>=20

Could you please elaborate what do you mean by
" common + protocol or protocol + common, not both please!"?
The order is same everywhere which is common + lane configuration for proto=
col 1
and then for protocol 2. For multiprotocol case, PHY configuration is based=
 on which
protocols are operating simultaneously. So e.g.
[TYPE_QSGMII][TYPE_PCIE] -> QSGMII configuration when other protocol is PCI=
e
Which might be different than
[TYPE_QSGMII][TYPE_*] -> QSGMII configuration with other protocol.

Thanks & regards,
Swapnil

> --
> ~Vinod