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References: <cover.1638402361.git.quic_vamslank@quicinc.com> <7e1805ef3f7cddc1222906d8b8e5b79548b46f63.1638402361.git.quic_vamslank@quicinc.com>
Subject: Re: [PATCH v6 2/5] clk: qcom: Add LUCID_EVO PLL type for SDX65
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
        manivannan.sadhasivam@linaro.org,
        Vamsi Krishna Lanka <quic_vamslank@quicinc.com>,
        Vinod Koul <vkoul@kernel.org>
To:     agross@kernel.org, bjorn.andersson@linaro.org, maz@kernel.org,
        mturquette@baylibre.com, quic_vamslank@quicinc.com,
        robh+dt@kernel.org, tglx@linutronix.de
Date:   Thu, 02 Dec 2021 16:18:43 -0800
User-Agent: alot/0.9.1
Message-Id: <20211203001844.78E7FC00446@smtp.kernel.org>
Precedence: bulk

Quoting quic_vamslank@quicinc.com (2021-12-01 16:21:32)
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alph=
a-pll.c
> index eaedcceb766f..e0c67b76d8ac 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -1741,35 +1760,47 @@ static int alpha_pll_lucid_5lpe_set_rate(struct c=
lk_hw *hw, unsigned long rate,
>                                           LUCID_5LPE_ALPHA_PLL_ACK_LATCH);
>  }
> =20
> +static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned =
long rate,
> +                                            unsigned long parent_rate, u=
nsigned long enable_vote_run)
> +{
> +        struct clk_alpha_pll_postdiv *pll =3D to_clk_alpha_pll_postdiv(h=
w);
> +       struct regmap *regmap =3D pll->clkr.regmap;

What's going on with the tabbing here?

> +        int i, val =3D 0, div, ret;

Do we need to initialize to 0?

> +        u32 mask;
> +
> +        /*
> +         * If the PLL is in FSM mode, then treat set_rate callback as a
> +         * no-operation.
> +         */
> +        ret =3D regmap_read(regmap, PLL_USER_CTL(pll), &val);
> +        if (ret)
> +                return ret;
> +
> +        if (val & enable_vote_run)
> +                return 0;
> +
> +        if (!pll->post_div_table) {
> +                pr_err("Missing the post_div_table for the PLL\n");

Probably useful to know which PLL is missing a table here.