Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: quoted-printable
In-Reply-To: <475a055e403762e54a1cae6c2c97d4ada6064607.1638402361.git.quic_vamslank@quicinc.com>
References: <cover.1638402361.git.quic_vamslank@quicinc.com> <475a055e403762e54a1cae6c2c97d4ada6064607.1638402361.git.quic_vamslank@quicinc.com>
Subject: Re: [PATCH v6 3/5] clk: qcom: Add SDX65 GCC support
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
        manivannan.sadhasivam@linaro.org,
        Vamsi Krishna Lanka <quic_vamslank@quicinc.com>
To:     agross@kernel.org, bjorn.andersson@linaro.org, maz@kernel.org,
        mturquette@baylibre.com, quic_vamslank@quicinc.com,
        robh+dt@kernel.org, tglx@linutronix.de
Date:   Thu, 02 Dec 2021 16:20:09 -0800
User-Agent: alot/0.9.1
Message-Id: <20211203002010.8225CC00446@smtp.kernel.org>
Precedence: bulk

Quoting quic_vamslank@quicinc.com (2021-12-01 16:21:33)
> +static struct clk_branch gcc_gp3_clk =3D {
> +       .halt_reg =3D 0x39000,
> +       .halt_check =3D BRANCH_HALT,
> +       .clkr =3D {
> +               .enable_reg =3D 0x39000,
> +               .enable_mask =3D BIT(0),
> +               .hw.init =3D &(struct clk_init_data){
> +                       .name =3D "gcc_gp3_clk",
> +                       .parent_data =3D &(const struct clk_parent_data){
> +                               .hw =3D &gcc_gp3_clk_src.clkr.hw,
> +                       },
> +                       .num_parents =3D 1,
> +                       .flags =3D CLK_SET_RATE_PARENT,
> +                       .ops =3D &clk_branch2_ops,
> +               },
> +       },
> +};
> +
> +static struct clk_branch gcc_pcie_0_clkref_en =3D {
> +       .halt_reg =3D 0x88004,
> +       /* The clock controller does not handle the status bit for

Please leave /* on it's own line for multiline comments.

> +        * the clocks with gdscs(powerdomains) in hw controlled mode
> +        * and hence avoid checking for the status bit of those clocks
> +        * by setting the BRANCH_HALT_DELAY flag */

And */ too

> +       .halt_check =3D BRANCH_HALT_DELAY,
> +       .clkr =3D {
> +               .enable_reg =3D 0x88004,
> +               .enable_mask =3D BIT(0),
> +               .hw.init =3D &(struct clk_init_data){
> +                       .name =3D "gcc_pcie_0_clkref_en",
> +                       .ops =3D &clk_branch2_ops,
> +               },
> +       },
> +};