Subject: Re: [PATCH 3/5] arm64: dts: ti: Add initial support for J721S2 SoC
To:     Aswath Govindraju <a-govindraju@ti.com>
CC:     Nishanth Menon <nm@ti.com>, Vignesh Raghavendra <vigneshr@ti.com>,
        Tero Kristo <kristo@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
References: <20211119133052.17793-1-a-govindraju@ti.com>
 <20211119133052.17793-4-a-govindraju@ti.com>
From:   Kishon Vijay Abraham I <kishon@ti.com>
Message-ID: <22180fe2-2b59-9558-4e5b-dc97bcf09c96@ti.com>
Date:   Fri, 3 Dec 2021 12:43:17 +0530
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Hi Aswath,

On 19/11/21 7:00 pm, Aswath Govindraju wrote:
> The J721S2 SoC belongs to the K3 Multicore SoC architecture platform,
> providing advanced system integration in automotive ADAS applications and
> industrial applications requiring AI at the network edge. This SoC extends
> the Jacinto 7 family of SoCs with focus on lowering system costs and power
> while providing interfaces, memory architecture and compute performance for
> single and multi-sensor applications.
> 
> Some highlights of this SoC are:
> 
> * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable
> dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x
> floating point Vector DSP.
> * 3D GPU: Automotive grade IMG BXS-4-64
> * Vision Processing Accelerator (VPAC) with image signal processor and
> Depth and Motion Processing Accelerator (DMPAC)
> * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface.
> * Two Ethernet ports with RGMII support.
> * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems,
> * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller,
> QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
> * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL
> management.
> * Chips and Media Wave521CL H.264/H.265 encode/decode engine
> 
> See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021)
> for further details: http://www.ti.com/lit/pdf/spruj28
> 
> Introduce basic support for the J721S2 SoC.
> 
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi    | 941 ++++++++++++++++++
>  .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi     | 302 ++++++
>  arch/arm64/boot/dts/ti/k3-j721s2.dtsi         | 189 ++++
>  3 files changed, 1432 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>  create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
>  create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2.dtsi
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> new file mode 100644
> index 000000000000..4fb629f1ec77
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -0,0 +1,941 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for J721S2 SoC Family Main Domain peripherals
> + *
> + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +#include <dt-bindings/mux/mux.h>
> +#include <dt-bindings/phy/phy.h>
> +#include <dt-bindings/mux/ti-serdes.h>

I don't see this being used right now. Better to add it when it's actually used.

Thanks
Kishon

> +
> +&cbass_main {
> +	msmc_ram: sram@70000000 {
> +		compatible = "mmio-sram";
> +		reg = <0x0 0x70000000 0x0 0x400000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0x0 0x0 0x70000000 0x400000>;
> +
> +		atf-sram@0 {
> +			reg = <0x0 0x20000>;
> +		};
> +
> +		tifs-sram@1f0000 {
> +			reg = <0x1f0000 0x10000>;
> +		};
> +
> +		l3cache-sram@200000 {
> +			reg = <0x200000 0x200000>;
> +		};
> +	};