Date:   Fri, 3 Dec 2021 16:26:00 +0530
From:   Pratyush Yadav <p.yadav@ti.com>
To:     Nishanth Menon <nm@ti.com>
CC:     Rob Herring <robh+dt@kernel.org>, Tero Kristo <kristo@kernel.org>,
        Vignesh Raghavendra <vigneshr@ti.com>,
        <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-omap@vger.kernel.org>, Peng Fan <peng.fan@nxp.com>
Subject: Re: [PATCH] arm64: dts: ti: k3-j721e: Fix the L2 cache sets
Message-ID: <20211203105558.eibfd2hamyjl2b6f@ti.com>
References: <20211113043639.4413-1-nm@ti.com>
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On 12/11/21 10:36PM, Nishanth Menon wrote:
> A72's L2 cache[1] on J721e[2] is 1MB. A53's L2 is fixed line length of
                                        ^^^

Do you mean A72? J721E does not have an A53 core, and this cache node is 
for A72 cores anyway.

Other than this,

Reviewed-by: Pratyush Yadav <p.yadav@ti.com>

> 64 bytes and 16-way set-associative cache structure.
> 
> 1MB of L2 / 64 (line length) = 16384 ways
> 16384 ways / 16 = 1024 sets
> 
> Fix the l2 cache-sets.
> 
> [1] https://developer.arm.com/documentation/100095/0003/Level-2-Memory-System/About-the-L2-memory-system
> [2] http://www.ti.com/lit/pdf/spruil1
> 
> Fixes: 2d87061e70de ("arm64: dts: ti: Add Support for J721E SoC")
> Reported-by: Peng Fan <peng.fan@nxp.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> index 214359e7288b..0f674bc8f1c7 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> @@ -88,7 +88,7 @@ L2_0: l2-cache0 {
>  		cache-level = <2>;
>  		cache-size = <0x100000>;
>  		cache-line-size = <64>;
> -		cache-sets = <2048>;
> +		cache-sets = <1024>;
>  		next-level-cache = <&msmc_l3>;
>  	};
>  

-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.