Date:   Fri, 3 Dec 2021 16:43:10 +0530
From:   Pratyush Yadav <p.yadav@ti.com>
To:     Nishanth Menon <nm@ti.com>
CC:     Rob Herring <robh+dt@kernel.org>, Tero Kristo <kristo@kernel.org>,
        Vignesh Raghavendra <vigneshr@ti.com>,
        <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-omap@vger.kernel.org>, Peng Fan <peng.fan@nxp.com>
Subject: Re: [PATCH] arm64: dts: ti: k3-am642: Fix the L2 cache sets
Message-ID: <20211203111308.zfxczgywmjzplbha@ti.com>
References: <20211113043635.4296-1-nm@ti.com>
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On 12/11/21 10:36PM, Nishanth Menon wrote:
> A53's L2 cache[1] on AM642[2] is 256KB. A53's L2 is fixed line length
> of 64 bytes and 16-way set-associative cache structure.

This time the commit message is correct :-)

Reviewed-by: Pratyush Yadav <p.yadav@ti.com>

> 
> 256KB of L2 / 64 (line length) = 4096 ways
> 4096 ways / 16 = 256 sets
> 
> Fix the l2 cache-sets.
> 
> [1] https://developer.arm.com/documentation/ddi0500/j/Level-2-Memory-System/About-the-L2-memory-system?lang=en
> [2] https://www.ti.com/lit/pdf/spruim2
> 
> Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC")
> Reported-by: Peng Fan <peng.fan@nxp.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-am642.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am642.dtsi b/arch/arm64/boot/dts/ti/k3-am642.dtsi
> index e2b397c88401..8a76f4821b11 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am642.dtsi
> @@ -60,6 +60,6 @@ L2_0: l2-cache0 {
>  		cache-level = <2>;
>  		cache-size = <0x40000>;
>  		cache-line-size = <64>;
> -		cache-sets = <512>;
> +		cache-sets = <256>;
>  	};
>  };

-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.