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Date:   Fri, 03 Dec 2021 11:42:10 +0000
From:   "Jiaxun Yang" <jiaxun.yang@flygoat.com>
To:     "Dave Hansen" <dave.hansen@intel.com>, x86@kernel.org
Cc:     "Thomas Gleixner" <tglx@linutronix.de>,
        "Ingo Molnar" <mingo@redhat.com>, bp@alien8.de,
        dave.hansen@linux.intel.com, hpa@zytor.com,
        chang.seok.bae@intel.com, linux-kernel@vger.kernel.org
Subject: Re: [RFC PATCH 00/10] x86: Allocate AVX512 xstate ondemand
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=E5=9C=A82021=E5=B9=B412=E6=9C=883=E6=97=A5=E5=8D=81=E4=BA=8C=E6=9C=88 =E4=
=B8=8A=E5=8D=8812:58=EF=BC=8CDave Hansen=E5=86=99=E9=81=93=EF=BC=9A
> On 12/2/21 4:45 PM, Jiaxun Yang wrote:
>> =E5=9C=A82021=E5=B9=B412=E6=9C=883=E6=97=A5=E5=8D=81=E4=BA=8C=E6=9C=88=
 =E4=B8=8A=E5=8D=8812:40=EF=BC=8CDave Hansen=E5=86=99=E9=81=93=EF=BC=9A
>>> On 12/2/21 4:36 PM, Jiaxun Yang wrote:
>>>> Also we are going to have heterogeneous processors that
>>>> only some cores support AVX512, it can be helpful when
>>>> dealing with such processors.
>>> Really?  Which x86 vendor is doing that?
>> Clear lower two bits of MSR 0xAF on Alder Lake give me some suprise :=
-)
>
> I honestly don't know what you're talking about.  Does poking that MSR
> allowing AVX512 instructions to be executed on cores where it was
> otherwise disabled?  That's entertaining, but it's far from "supported"
> or even support*able* in Linux.

If it's improper I'll drop the statement in commit message :-)

Yep, I'm entertaining with kernel hackcing.

Thanks

--=20
- Jiaxun