Date:   Fri, 03 Dec 2021 14:12:07 +0000
To:     Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>
From:   Adam Wujek <dev_public@wujek.eu>
Cc:     Adam Wujek <dev_public@wujek.eu>, linux-clk@vger.kernel.org,
        linux-kernel@vger.kernel.org
Reply-To: Adam Wujek <dev_public@wujek.eu>
Subject: [PATCH] clk: si5341: fix reported clk_rate when output divider is 2
Message-ID: <20211203141125.2447520-1-dev_public@wujek.eu>
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Transfer-Encoding: quoted-printable
Precedence: bulk

SI5341_OUT_CFG_RDIV_FORCE2 shall be checked first to distinguish whether
a divider for a given output is set to 2 (SI5341_OUT_CFG_RDIV_FORCE2
is set) or the output is disabled (SI5341_OUT_CFG_RDIV_FORCE2 not set,
SI5341_OUT_R_REG is set 0).
Before the change, divider set to 2 (SI5341_OUT_R_REG set to 0) was
interpreted as output is disabled.

Signed-off-by: Adam Wujek <dev_public@wujek.eu>
---
 drivers/clk/clk-si5341.c | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/clk-si5341.c b/drivers/clk/clk-si5341.c
index b7641abe6747..15b1c90cafe5 100644
--- a/drivers/clk/clk-si5341.c
+++ b/drivers/clk/clk-si5341.c
@@ -798,6 +798,15 @@ static unsigned long si5341_output_clk_recalc_rate(str=
uct clk_hw *hw,
 =09u32 r_divider;
 =09u8 r[3];

+=09err =3D regmap_read(output->data->regmap,
+=09=09=09SI5341_OUT_CONFIG(output), &val);
+=09if (err < 0)
+=09=09return err;
+
+=09/* If SI5341_OUT_CFG_RDIV_FORCE2 is set, r_divider is 2 */
+=09if (val & SI5341_OUT_CFG_RDIV_FORCE2)
+=09=09return parent_rate / 2;
+
 =09err =3D regmap_bulk_read(output->data->regmap,
 =09=09=09SI5341_OUT_R_REG(output), r, 3);
 =09if (err < 0)
@@ -814,13 +823,6 @@ static unsigned long si5341_output_clk_recalc_rate(str=
uct clk_hw *hw,
 =09r_divider +=3D 1;
 =09r_divider <<=3D 1;

-=09err =3D regmap_read(output->data->regmap,
-=09=09=09SI5341_OUT_CONFIG(output), &val);
-=09if (err < 0)
-=09=09return err;
-
-=09if (val & SI5341_OUT_CFG_RDIV_FORCE2)
-=09=09r_divider =3D 2;

 =09return parent_rate / r_divider;
 }
--
2.25.1